Silicon Design Verification Engineer, TPU, Google Cloud
Description For Silicon Design Verification Engineer, TPU, Google Cloud
Google is seeking a Silicon Design Verification Engineer for their TPU (Tensor Processing Unit) team within Google Cloud. This role is crucial in shaping the future of AI/ML hardware acceleration, working on cutting-edge TPU technology that powers Google's most demanding AI/ML applications. The position involves being part of a diverse team developing custom silicon solutions for Google's TPU.
The role encompasses the full verification life cycle, from planning to coverage closure, with a focus on meeting AI/ML performance targets. You'll build robust, constrained-random verification environments to ensure reliability of AI/ML workloads on TPU hardware. The position requires collaboration with design and verification engineers on active projects.
As part of the Technical Infrastructure team, you'll contribute to the architecture that keeps Google's services running. The team is responsible for developing and maintaining data centers and building next-generation Google platforms. The role combines technical expertise in hardware verification with the opportunity to impact Google's AI/ML infrastructure.
The ideal candidate should have strong experience in verification methodology, particularly UVM, and expertise in SystemVerilog and SVA. Knowledge of AI/ML Accelerators or vector processing units is highly valued. The position offers the opportunity to work on innovative technology that powers products used by millions worldwide.
Google offers an inclusive work environment, committed to equal opportunity and building a representative workforce. The company provides comprehensive benefits and supports workplace diversity and accommodation needs.
Responsibilities For Silicon Design Verification Engineer, TPU, Google Cloud
- Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Measure to identify verification holes and to show progress towards tape-out
- Create a constrained-random verification environment using SystemVerilog and Universal verification methodology (UVM)
Requirements For Silicon Design Verification Engineer, TPU, Google Cloud
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 4 years of experience with verification methodology such as Universal verification methodology (UVM)
- 2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
- Experience with SystemVerilog, SVA, and functional coverage
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