Silicon Digital Design Engineer
Description For Silicon Digital Design Engineer
Google is seeking a Silicon Digital Design Engineer to join their hardware team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role involves RTL design development of security IP and subsystems, including microarchitecture, RTL coding, and various optimizations. The position requires expertise in digital logic design, RTL concepts, and experience with languages like Verilog or SystemVerilog. You'll work on innovative hardware solutions that power Google's products, collaborating with cross-functional teams to deliver high-quality designs. The role combines Google's strengths in AI, Software, and Hardware to create impactful technological experiences. You'll be responsible for various aspects of chip design, from micro-architecture to power performance optimization, contributing to Google's mission of organizing world's information and making it universally accessible.
Responsibilities For Silicon Digital Design Engineer
- Work with ASIC RTL Engineers on sub-system and chip-level integration activities including plan tasks, hold code and design reviews, and contribute on sub-system/chip-level integration
- Interact closely with the Architecture team and develop implementation strategies to meet quality, schedule, and power performance and area for sub-system/chip-level integration
- Interact closely with the Subsystem team and plan SOC milestones, plan quality checks as part of SOC milestones, and guide subsystem teams with SOC level requirements
- Work closely with the cross-functional team of verification, design for test, physical design, emulation, and software teams to make design decisions and represent project status throughout the development process
Requirements For Silicon Digital Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- Experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power, and low-power design techniques
- Experience with a scripting language such as Perl or Python
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