Silicon Layout Engineer

Google's Raxium display group is at the forefront of revolutionary semiconductor materials display technology, specifically focused on augmented reality (AR) and light-field display applications. As a Silicon Layout Engineer, you'll join a dynamic team working on cutting-edge display technology at their state-of-the-art compound semiconductor fab in Silicon Valley. The role demands expertise in analog circuit design and layout techniques, with a focus on advanced process nodes (22nm and below).

You'll be responsible for delivering high-performance analog layout designs, working closely with circuit designers to meet performance targets, and ensuring compliance with manufacturing requirements through comprehensive verification checks. The position requires strong technical skills in industry-standard layout tools and verification methodologies, as well as the ability to contribute to improving layout methodologies and best practices.

The role offers competitive compensation ($177,000-$266,000) plus bonus, equity, and comprehensive benefits. This is an excellent opportunity for experienced professionals who want to be part of Google's innovative technology development, specifically in the AR/VR space. You'll work with extraordinarily creative and talented teams, developing products that will impact millions of users.

The ideal candidate will have 8+ years of experience in analog circuit design principles and layout techniques, strong problem-solving abilities, and excellent communication skills. This position offers the chance to work on disruptive display technology while being backed by Google's resources and expertise. If you're passionate about pushing the boundaries of display technology and want to be part of shaping the future of AR/VR interfaces, this role presents an exciting career opportunity.