Silicon Layout Engineer

Google's Raxium display group is revolutionizing semiconductor materials display technology for AR and light-field applications. As a Silicon Layout Engineer, you'll join an innovative team developing cutting-edge display products at their state-of-the-art compound semiconductor fab in Silicon Valley. The role involves delivering high-performance analog layout design, performing verification checks, and developing efficient methodologies.

You'll work with advanced process nodes (22nm and below), utilizing your expertise in analog circuit design principles and layout techniques. The position requires proficiency with industry-standard tools like Cadence Virtuoso and Mentor Graphics Calibre, along with scripting abilities in languages such as Python and TCL for layout automation.

The role offers competitive compensation ($177,000-$266,000) plus bonus, equity, and comprehensive benefits. You'll be part of Google's extraordinarily creative and talented team, developing products used by millions. The position demands strong technical skills, including parasitic extraction and analysis knowledge, verification tools expertise, and understanding of reliability considerations.

This is an excellent opportunity for experienced professionals who want to impact next-generation display markets. You'll collaborate with circuit designers, optimize layouts for performance and power, and contribute to best practices. The role combines technical expertise with innovation, offering the chance to work on revolutionary technology while being supported by Google's resources and culture of excellence.

Join a team that's pushing the boundaries of display technology, bringing users closer to a seamless integration of digital and physical realms. Your work will directly influence the future of AR and display technology, making this an exciting opportunity for those passionate about innovation and technical excellence.