Silicon Low Power Design Engineer, TPU, Google Cloud
Description For Silicon Low Power Design Engineer, TPU, Google Cloud
Google is seeking a Silicon Low Power Design Engineer to join their TPU team within Google Cloud. This role focuses on developing cutting-edge SoCs used to accelerate machine learning computation in data centers. As part of a diverse team, you'll be responsible for pushing boundaries in custom silicon solutions that power Google's direct-to-consumer products. The position requires expertise in ASIC/SoC development with a strong focus on power optimization.
The role involves collaborating with various teams including architecture, verification, power and performance, and physical design to deliver high-quality designs for next-generation data center accelerators. You'll be working on solving technical problems with innovative and practical logic solutions, while evaluating design options considering complexity, performance, power, and area constraints.
As part of Google's Technical Infrastructure team, you'll contribute to the architecture that keeps Google's services running efficiently. The team takes pride in being the engineers' engineers, working on maintaining data centers and building next-generation Google platforms. This position offers the opportunity to work on projects that directly impact millions of users worldwide through Google's product portfolio.
The ideal candidate should have strong experience in power management schemes, UPF definition, and power estimation. Knowledge of programming languages like Python, C/C++, or Perl, along with experience in SoC designs and integration flows would be beneficial. The role requires a collaborative mindset as you'll be working with cross-functional teams to ensure smooth project execution and delivery.
Responsibilities For Silicon Low Power Design Engineer, TPU, Google Cloud
- Participate in defining power management schemes and low power modes
- Create power specifications and UPF definition for SoC and subsystems
- Perform power estimation, roll, up and tracking through all phases of the project
- Run power optimization tools, suggest ways to improve power, and drive convergence
- Work with cross-functional teams for smooth handoff of power intent and power projections
Requirements For Silicon Low Power Design Engineer, TPU, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in ASIC/SoC development, with a focus on Power optimization
- Experience handling Low Power schemes, power roll up, and power estimations
- Experience with ASIC design verification, synthesis, and timing analysis
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