Silicon Networking RTL Design Engineer
Description For Silicon Networking RTL Design Engineer
Google is seeking a Silicon Networking RTL Design Engineer to join their hardware development team. This role focuses on developing custom silicon solutions that power Google's direct-to-consumer products and data center accelerators. As part of this position, you'll work on ASIC development, collaborating with cross-functional teams in architecture, verification, power and performance, and physical design.
The role requires expertise in RTL implementation, micro-architecture design, and networking protocols. You'll be responsible for developing and optimizing hardware solutions that improve traffic efficiency in data centers. This involves working with Verilog/SystemVerilog, VHDL, and various design verification tools.
The ideal candidate should have strong experience in ASIC development, networking domains, and hardware design. You'll contribute to Google's mission of creating radically helpful experiences by combining the best of Google AI, Software, and Hardware. This is an opportunity to shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Working at Google, you'll be part of a diverse team that pushes boundaries and develops solutions used by millions worldwide. The role offers the chance to work on cutting-edge technology while collaborating with industry experts. You'll be involved in all aspects of the design process, from specification to delivery, making a direct impact on Google's infrastructure and products.
If you're passionate about hardware design, have experience in networking protocols, and want to work on technology that powers one of the world's largest technology companies, this role offers an exciting opportunity to make a significant impact.
Responsibilities For Silicon Networking RTL Design Engineer
- Own Register-Transfer Level (RTL) implementation of Internet Protocols (IPs) and subsystems in Networking domain
- Work with design team members to close feature definitions and develop micro-architecture specifications
- Participate in design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams
- Work on Power, Performance and Area improvements for the domains owned
Requirements For Silicon Networking RTL Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 4 years of experience in Application-specific integrated circuit (ASIC) development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL)
- Experience in micro-architecture and design of Internet Protocols (IPs) and Subsystems
- Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience in Networking domain like Packet processing, bandwidth management, congestion control, etc.
- Experience with scripting languages (e.g., Python or Perl)
- Knowledge of bus architectures, fabrics, processor design, or memory hierarchies
- Knowledge of high performance and low power design techniques
Jobs Related To Google Silicon Networking RTL Design Engineer
