Silicon Security Test and Verification Engineer
Description For Silicon Security Test and Verification Engineer
Google is seeking a Silicon Security Test and Verification Engineer to join their Hardware Testing Engineering team. This role is crucial in ensuring the reliability of Google's custom-designed machines, which form one of the largest computing infrastructures globally. The position involves working in R&D labs, designing test equipment for prototypes, and developing scalable testing protocols.
The ideal candidate will have a strong background in electrical engineering with expertise in SOC/IP DV and verification methodologies. You'll be working with cutting-edge technology, collaborating closely with design engineers to improve hardware quality and reliability. The role requires proficiency in various technical areas including ARM security architecture, verification tools, and scripting languages.
As part of Google's mission to organize the world's information and make it universally accessible, you'll be contributing to the development of radically helpful experiences by combining the best of Google AI, Software, and Hardware. The position offers the opportunity to work on innovative technologies that aim to make people's lives better through technology.
Key responsibilities include collaborating with internal teams on Silicon OTP fusing and provisioning flows, debugging at various levels, and delivering automation flows. The role requires both technical expertise and the ability to work independently while maintaining strong collaborative relationships with SoC Development teams.
This position is perfect for someone who is passionate about hardware testing, has a strong technical foundation, and wants to contribute to Google's cutting-edge technology infrastructure. You'll be part of a team that's directly responsible for ensuring the quality and reliability of Google's hardware systems.
Responsibilities For Silicon Security Test and Verification Engineer
- Collaborate with internal design teams to define requirements and support Silicon OTP fusing, repair, and provisioning flows
- Simulate and debug at RTL/Gate level/Timing, ATE/Bench pattern generation with target coverage
- Work independently with simulators and debug tools including VCS, NCVerilog, and Novas
- Understand SoC level DV/UVM environment and JTAG/APB/AHB/AXI based protocols
- Deliver automation flows using scripting languages such as Python, Perl, Skill, and TCL
Requirements For Silicon Security Test and Verification Engineer
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 2 years of experience in SOC/IP DV
- Experience with verification methodology such as SV and UVM
- Experience in ARM security architecture
- Familiarity with SoC level DV/UVM environment
- Knowledge of JTAG/APB/AHB/AXI based protocols
- HDL (Verilog/VHDL), HVL (System Verilog, OVM, ARM-C), and SVA experience
- Knowledge of ATE pattern generation/conversion
- Ability to write scripts in Perl, Python or bash
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