Silicon Senior Design Verification Engineer, Security
Description For Silicon Senior Design Verification Engineer, Security
Google is seeking a Senior Design Verification Engineer to join their Security team in Bengaluru. This role is part of Google's initiative to develop custom silicon solutions that power their direct-to-consumer products. The position requires expertise in verification methodologies, particularly UVM and System Verilog, with a focus on security design blocks and subsystems.
The ideal candidate will have 5+ years of experience and a strong background in electrical engineering or computer science. They will work closely with designers, architects, and stakeholders to develop comprehensive test plans and verification environments. The role involves understanding complex security requirements and implementing verification scenarios for security IP and subsystems.
As part of Google's hardware team, you'll contribute to innovations that impact millions of users worldwide. The team combines Google's strengths in AI, software, and hardware to create next-generation computing experiences. You'll be responsible for creating and enhancing verification environments, ensuring the quality and security of hardware designs, and serving as the primary point of contact for functional verification.
This is an excellent opportunity for someone passionate about hardware security and verification to work on cutting-edge technology at one of the world's leading tech companies. You'll be part of a diverse team that pushes boundaries and shapes the future of Google's hardware experiences, focusing on unparalleled performance, efficiency, and integration.
The role offers the chance to work on products that directly impact users' lives, with access to Google's vast resources and innovative technology stack. You'll be at the forefront of developing secure hardware solutions that power Google's consumer products, making computing faster, seamless, and more powerful.
Responsibilities For Silicon Senior Design Verification Engineer, Security
- Work with designer, architects and other stakeholders to come up with detailed test plans, dependencies and deliverables
- Plan the verification of security design blocks by fully understanding the design specification, security requirements and interacting with architecture and design engineers to identify important verification scenarios
- Create and enhance constrained-random verification environments using System Verilog and UVM
- Be the primary point of contact for functional verification of the IP for cross-functional teams
Requirements For Silicon Senior Design Verification Engineer, Security
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience with verification methodologies and languages such as UVM and System Verilog
- Experience developing and maintaining verification testbenches, test cases, and test environments
- Experience with low power, debug, performance verification and use cases verification
- Experience with Security IP and subsystems
- Experienced in ARM or RISC-V CPU based subsystem verification
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