Silicon Senior Design Verification Engineer, TPU, Google Cloud
Description For Silicon Senior Design Verification Engineer, TPU, Google Cloud
Google is seeking a Senior Design Verification Engineer to join their TPU (Tensor Processing Unit) team within Google Cloud. This role is crucial in shaping the future of AI/ML hardware acceleration, working on cutting-edge TPU technology that powers Google's most demanding AI/ML applications. The position involves verifying complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. You'll be part of the Technical Infrastructure team, responsible for building and maintaining Google's platforms and data centers. The role requires expertise in verification methodologies, SystemVerilog, and experience with AI/ML Accelerators. You'll collaborate with design engineers, create verification environments, and ensure the functionality of design blocks through comprehensive testing and coverage analysis. This is an opportunity to contribute to innovative products used by millions while working with industry-leading tools and technologies in the heart of Google's AI infrastructure.
Responsibilities For Silicon Senior Design Verification Engineer, TPU, Google Cloud
- Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Close coverage measures to identify verification holes and to show progress towards tape-out
Requirements For Silicon Senior Design Verification Engineer, TPU, Google Cloud
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 5 years of experience with verification methodology such as UVM/OVM/VMM
- 3 years of experience in the verification of IP designs such as CPU, Peripherals, PMU, etc.
- Experience with SystemVerilog, SVA and functional coverage
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