Silicon SoC RTL Design/Integration Engineer
Description For Silicon SoC RTL Design/Integration Engineer
Google is seeking a Silicon SoC RTL Design/Integration Engineer to join their Hardware Testing Engineering team. This role is crucial in developing and maintaining Google's custom-designed machines that power one of the world's largest computing infrastructures.
As a member of the Digital Design team, you'll be instrumental in crafting architecture for current and future ASIC projects, focusing on networking solutions. You'll collaborate closely with verification and validation teams to ensure proper feature testing, while working with Google product teams to align microarchitecture designs with their goals.
The position requires expertise in ASIC development, networking protocols, and design verification. You'll be responsible for defining and managing microarchitecture for subsystems and SoCs, working with physical design teams, and driving architecture validation with both internal and external stakeholders.
This role offers the opportunity to work at the forefront of hardware innovation, developing next-generation technologies that impact how users connect and interact with information. You'll be part of Google's Technical Infrastructure team, which takes pride in building and maintaining the architecture that makes Google's product portfolio possible.
The ideal candidate should have a strong background in electrical engineering or computer science, with experience in ASIC development using Verilog/SystemVerilog, VHDL, or Chisel. Knowledge of networking protocols, design verification, and testing is essential. Experience with scripting languages like Python and understanding of SoC designs and integration flows would be advantageous.
Join Google's team of engineers' engineers who are passionate about pushing technological boundaries and maintaining the high-performance infrastructure that powers Google's services. This role offers the chance to work on cutting-edge hardware solutions while collaborating with diverse teams across the organization.
Responsibilities For Silicon SoC RTL Design/Integration Engineer
- Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design
- Manage the architecture and microarchitecture of current and future generations of ASIC
- Work closely with Physical Design teams to ensure success. Consolidate demands from Verification, Manufacturing and Product teams
- Help drive internal and external users to vet architecture ideas
Requirements For Silicon SoC RTL Design/Integration Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 1 year of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel
- Experience in networking, including working with Ethernet, TCP/IP, buffering, queueing, and scheduling
- Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
Benefits For Silicon SoC RTL Design/Integration Engineer
- Equal opportunity employer
- Inclusive work environment
- Comprehensive health benefits
- Parental leave benefits
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