Silicon SoC RTL Design/Integration Engineer
Description For Silicon SoC RTL Design/Integration Engineer
Google Cloud is seeking a Silicon SoC RTL Design/Integration Engineer to join their Hardware Testing Engineering team. This role is crucial in developing and maintaining Google's custom-designed machines, which form one of the world's largest computing infrastructures.
As a member of the Digital Design team, you'll be instrumental in crafting architecture for current and future ASIC projects, focusing on networking solutions. You'll collaborate closely with verification and validation teams to ensure proper feature testing, while working with Google product teams to align microarchitecture designs with their objectives.
The position involves working with cutting-edge hardware in Google's R&D lab, where you'll design test equipment for prototypes and develop scalable testing protocols. You'll have the opportunity to influence hardware designs, ensuring they meet Google's rigorous quality and reliability standards.
Key responsibilities include defining subsystem microarchitecture, managing current and future ASIC generations, and coordinating with Physical Design teams. You'll need expertise in ASIC development, networking protocols, and verification processes. The role offers the chance to work on innovative technologies that impact how users interact with information globally.
This is an excellent opportunity for someone with a background in electrical or computer engineering who wants to work at the forefront of hardware development. You'll be part of Google's Technical Infrastructure team, helping to build and maintain the architecture that powers Google's extensive product portfolio. The role combines technical expertise with collaborative teamwork, making it ideal for engineers who enjoy both detailed technical work and cross-functional collaboration.
Responsibilities For Silicon SoC RTL Design/Integration Engineer
- Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design
- Manage the architecture and microarchitecture of current and future generations of ASIC
- Work closely with Physical Design teams to ensure success. Consolidate demands from Verification, Manufacturing and Product teams
- Help drive internal and external users to vet architecture ideas
Requirements For Silicon SoC RTL Design/Integration Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 1 year of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel
- Experience in networking, including working with Ethernet, TCP/IP, buffering, queueing, and scheduling
- Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
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