SoC and IP Design Engineer, Google Cloud
Description For SoC and IP Design Engineer, Google Cloud
Google Cloud is seeking a skilled SoC and IP Design Engineer to join their Technical Infrastructure team. This role focuses on developing custom silicon solutions that power Google's direct-to-consumer products. As part of the team, you'll work on innovative hardware experiences that serve millions of users worldwide. The position involves working with cutting-edge technology in Google's data centers and platforms, contributing to the architecture that keeps Google's services running smoothly. You'll be responsible for SoC/block level design, RTL development, and working with various verification and quality tools. The role requires expertise in digital logic design, verification, and optimization techniques. You'll collaborate with cross-functional teams across multiple locations, participating in all aspects of the silicon development process from design to bring-up. This is an opportunity to shape the future of Google's hardware infrastructure while working with state-of-the-art technology and talented engineers.
Responsibilities For SoC and IP Design Engineer, Google Cloud
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure and ASIC silicon bring-up
- Participate in test plan and coverage analysis of the block and SoC level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For SoC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
- Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.)
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