SOC Power Estimation Engineer
Description For SOC Power Estimation Engineer
Google is seeking a SOC Power Estimation Engineer to join their hardware team in Bengaluru. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. As a Power Estimation Engineer, you'll be responsible for pre-silicon power estimation and analysis, working with cutting-edge power estimation tools at both RTL and Netlist levels.
The position requires expertise in low power RTL and physical design techniques, along with proficiency in scripting languages like Python. You'll collaborate with architecture design teams to define scenarios and operating conditions that reflect real-world usage of IPs. Your work will directly impact the power efficiency of Google's hardware products.
The ideal candidate should have a bachelor's degree in Electrical Engineering, Computer Engineering, or related field, with at least 2 years of relevant experience. Strong problem-solving skills and the ability to work both independently and in teams are essential. Experience with SoC architecture, power management, and clocking architecture is highly valued.
This is an exciting opportunity to be part of Google's innovative hardware team, contributing to products used by millions worldwide. You'll work at the intersection of AI, software, and hardware, helping to create the next generation of efficient and powerful computing solutions. The role offers the chance to work with cutting-edge technology while collaborating with diverse, talented teams to push the boundaries of what's possible in hardware design.
Responsibilities For SOC Power Estimation Engineer
- Drive pre-silicon power estimation and analysis using power estimation tools both at Register-Transfer Level (RTL) and Netlist level
- Develop methodologies around power estimation tools and incorporate best practices to improve the power estimation
- Drive Power estimation and what-if analysis for IP(s) and SubSystem(s) and drive closure of projections vs targets gaps
- Analyze power estimation reports to identify power-saving opportunities and influence both the physical design aspect and the u-arch design aspects of the design for power reduction
- Collaborate with the Arch Design team to define the right definition of scenarios and operating conditions to estimate the use-case power for the IP which reflects the real world usage of the IP
Requirements For SOC Power Estimation Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 2 years of experience with low power RTL and physical design techniques
- Experience with scripting languages (e.g., Python, Perl)
- Experience in System on a Chip (SoC) architecture, power management architecture, clocking architecture
- Experience with RTL level power estimation/analysis tools
- Ability to work separately and as part of a team
- Excellent problem-solving and investigative skills
- Excellent communication and teamwork skills
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