SOC Power Estimation Engineer
Description For SOC Power Estimation Engineer
Google is seeking a SOC Power Estimation Engineer to join their hardware team, focusing on developing custom silicon solutions for direct-to-consumer products. This role combines hardware expertise with Google's cutting-edge technology to create innovative solutions that power millions of users worldwide.
The position requires strong expertise in power estimation and analysis, particularly in SoC architecture and RTL design. You'll work with advanced power estimation tools, develop methodologies, and collaborate with various teams to optimize power consumption in Google's hardware products. This role is perfect for someone who combines technical expertise in hardware design with analytical skills and a collaborative mindset.
As a Power Estimation Engineer, you'll be at the forefront of Google's hardware innovation, working on projects that directly impact product performance and efficiency. You'll have the opportunity to influence both physical design and micro-architecture aspects, contributing to power optimization strategies that enhance Google's hardware portfolio.
The role offers the chance to work with Google's industry-leading teams, access to cutting-edge technology, and the opportunity to contribute to products used by millions. You'll be part of Google's mission to create radically helpful experiences through the perfect blend of AI, software, and hardware. This position is ideal for someone passionate about hardware design, power optimization, and creating impactful consumer technology solutions.
Responsibilities For SOC Power Estimation Engineer
- Drive pre-silicon power estimation and analysis using power estimation tools both at Register-Transfer Level (RTL) and Netlist level
- Develop methodologies around power estimation tools and incorporate best practices to improve the power estimation
- Drive Power estimation and what-if analysis for IP(s) and SubSystem(s) and drive closure of projections vs targets gaps
- Analyze power estimation reports to identify power-saving opportunities and influence both the physical design aspect and the u-arch design aspects of the design for power reduction
- Collaborate with the Arch Design team to define the right definition of scenarios and operating conditions to estimate the use-case power for the IP which reflects the real world usage of the IP
Requirements For SOC Power Estimation Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 2 years of experience with low power RTL and physical design techniques
- Experience with scripting languages (e.g., Python, Perl)
- Experience in System on a Chip (SoC) architecture, power management architecture, clocking architecture
- Experience with RTL level power estimation/analysis tools
- Ability to work separately and as part of a team
- Excellent problem-solving and investigative skills
- Excellent communication and teamwork skills
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