SOC Power Estimation Engineer
Description For SOC Power Estimation Engineer
Google is seeking a SOC Power Estimation Engineer to join their hardware team, focusing on developing custom silicon solutions for direct-to-consumer products. This role combines hardware expertise with Google's cutting-edge technology to create innovative solutions that power millions of users worldwide.
The position requires strong expertise in power estimation and analysis at both RTL and Netlist levels, with a focus on developing and implementing methodologies for efficient power estimation. You'll work with state-of-the-art tools and collaborate with architecture design teams to optimize power consumption in System on Chip (SoC) designs.
As a member of Google's hardware team, you'll contribute to the development of next-generation hardware experiences, focusing on performance, efficiency, and integration. The role offers an opportunity to work with diverse teams, pushing boundaries in custom silicon development and directly impacting Google's consumer products.
Key responsibilities include driving pre-silicon power estimation, developing methodologies for power analysis, and collaborating with various teams to optimize power consumption. You'll need a bachelor's degree in a relevant field, experience with low power RTL and physical design techniques, and proficiency in scripting languages.
The ideal candidate will possess excellent problem-solving abilities, strong communication skills, and experience in SoC architecture and power management. This role offers the chance to work on cutting-edge technology while being part of Google's mission to organize world's information and make it universally accessible.
Google provides an inclusive work environment, emphasizing diversity and equal opportunity. The company is committed to building a workforce that represents its global user base, fostering a culture of belonging and innovation.
Responsibilities For SOC Power Estimation Engineer
- Drive pre-silicon power estimation and analysis using power estimation tools both at Register-Transfer Level (RTL) and Netlist level
- Develop methodologies around power estimation tools and incorporate best practices to improve the power estimation
- Drive Power estimation and what-if analysis for IP(s) and SubSystem(s) and drive closure of projections vs targets gaps
- Analyze power estimation reports to identify power-saving opportunities and influence both the physical design aspect and the u-arch design aspects of the design for power reduction
- Collaborate with the Arch Design team to define the right definition of scenarios and operating conditions to estimate the use-case power for the IP which reflects the real world usage of the IP
Requirements For SOC Power Estimation Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 2 years of experience with low power RTL and physical design techniques
- Experience with scripting languages (e.g., Python, Perl)
- Experience in System on a Chip (SoC) architecture, power management architecture, clocking architecture
- Experience with RTL level power estimation/analysis tools
- Ability to work separately and as part of a team
- Excellent problem-solving and investigative skills
- Excellent communication and teamwork skills
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