SoC RTL Design Engineer
Description For SoC RTL Design Engineer
Google is seeking a SoC RTL Design Engineer to join their Devices & Services team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role combines hardware expertise with Google's AI and software capabilities to create innovative user experiences. The position involves working on cutting-edge hardware development, contributing to microarchitecture definition, RTL coding, and cross-functional collaboration.
The ideal candidate will be part of a diverse team that pushes boundaries in hardware development, working on products that impact millions of users worldwide. You'll be involved in the complete design cycle, from architecture definition to implementation, ensuring high-quality deliverables that meet schedule requirements.
Google's Devices & Services team is dedicated to creating radically helpful experiences for users through the combination of AI, Software, and Hardware. The team focuses on advancing form factors, improving interaction methods, and finding new ways to capture and sense the world around us.
This role offers the opportunity to work with cutting-edge technology in custom silicon development, collaborate with talented cross-functional teams, and contribute to products that directly impact users' daily lives. The position requires strong technical skills in RTL design, verification, and system architecture, combined with the ability to work effectively in a collaborative environment.
As part of Google's commitment to diversity and inclusion, they provide equal employment opportunities and welcome candidates from all backgrounds. The company offers a culture of belonging and supports work-life balance, though specific benefits are not mentioned in the job posting.
Responsibilities For SoC RTL Design Engineer
- Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design
- Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks
- Work closely with the cross-functional team of Architecture, Verification, Design for Test, Physical Design, and Software teams to make design decisions
- Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc
Requirements For SoC RTL Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
- 3 years of experience in RTL coding using Verilog or Systemverilog language
- Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification
- English proficiency is required
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