SoC RTL Design Engineer
Description For SoC RTL Design Engineer
Google is seeking a SoC RTL Design Engineer to join their Devices & Services team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role combines hardware expertise with Google's innovative approach to create next-generation hardware experiences.
The position requires strong technical expertise in RTL design and microarchitecture development, with the successful candidate working on cutting-edge hardware solutions that power Google's consumer products. You'll be part of a diverse team that pushes boundaries in silicon development, contributing to products used by millions worldwide.
Key responsibilities include defining microarchitecture for Subsystems/SoCs, performing RTL coding, and collaborating with cross-functional teams. The role demands expertise in Verilog/SystemVerilog, experience with various verification methodologies, and strong system-level understanding of hardware design.
The ideal candidate will have at least 3 years of relevant experience and a strong educational background in Electrical Engineering or Computer Science. Knowledge of process cores, interconnects, debug and trace, security, and other hardware-specific areas is highly valued.
This position offers the opportunity to work at one of the world's leading technology companies, contributing to innovative hardware solutions that directly impact user experiences. You'll be part of Google's mission to organize the world's information and make it universally accessible, while working with cutting-edge technology and talented professionals in the hardware development field.
Responsibilities For SoC RTL Design Engineer
- Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design
- Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks
- Work closely with the cross-functional team of Architecture, Verification, Design for Test, Physical Design, and Software teams to make design decisions
- Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc
Requirements For SoC RTL Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
- 3 years of experience in RTL coding using Verilog or Systemverilog language
- Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification
- English proficiency is a requirement
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