SoC RTL Design Engineer
Description For SoC RTL Design Engineer
Google's Devices & Services team is seeking a skilled SoC RTL Design Engineer to join their diverse team that pushes boundaries in developing custom silicon solutions. This role is integral to powering the future of Google's direct-to-consumer products, contributing to innovations that impact millions of users worldwide. The position requires expertise in RTL coding, microarchitecture definition, and cross-functional collaboration.
As a SoC RTL Design Engineer, you'll be responsible for defining and implementing microarchitecture for Subsystems and SoCs, working with various teams to ensure quality deliverables. The role involves detailed technical work including RTL coding, simulation debugging, and various system checks. You'll work closely with Architecture, Verification, Design for Test, Physical Design, and Software teams to make crucial design decisions.
The ideal candidate should have a strong background in Electrical Engineering or Computer Science, with at least 3 years of experience in RTL coding using Verilog or Systemverilog. Knowledge of process cores, interconnects, debug and trace, security, interrupts, and other related areas is highly valued. This position offers the opportunity to shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google offers a collaborative environment where diversity is celebrated and equal opportunity is paramount. The company is committed to creating a culture of belonging and provides comprehensive support for its employees. This role presents an exciting opportunity to work on cutting-edge technology while contributing to products that make a real difference in people's lives.
Responsibilities For SoC RTL Design Engineer
- Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design
- Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks
- Work closely with the cross-functional team of Architecture, Verification, Design for Test, Physical Design, and Software teams to make design decisions
- Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc
Requirements For SoC RTL Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
- 3 years of experience in RTL coding using Verilog or Systemverilog language
- Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification
- English proficiency is a requirement
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