SoC RTL Design Engineer
Description For SoC RTL Design Engineer
Google is seeking a SoC RTL Design Engineer to join their Devices & Services team, focusing on developing custom silicon solutions for Google's direct-to-consumer products. This role combines hardware expertise with Google's innovative approach to create next-generation hardware experiences.
The position requires strong technical expertise in RTL design and microarchitecture development, with the engineer being responsible for defining and implementing crucial subsystems within Google's SoC designs. The ideal candidate will have a solid foundation in electrical engineering or computer science, with specific expertise in RTL coding using Verilog or SystemVerilog.
As part of Google's hardware team, you'll work on products that impact millions of users worldwide, focusing on delivering unparalleled performance, efficiency, and integration. The role involves close collaboration with cross-functional teams, including Architecture, Verification, Design for Test, Physical Design, and Software teams.
The position offers the opportunity to work on cutting-edge hardware development at one of the world's leading technology companies. You'll be contributing to Google's mission of organizing the world's information while working on innovative hardware solutions that power their consumer products.
Key responsibilities include defining microarchitecture for subsystems, performing RTL coding, conducting various technical checks and simulations, and creating detailed design documentation. The role requires both technical expertise and the ability to work effectively in a collaborative environment.
Google offers a diverse and inclusive work environment, with a strong commitment to equal opportunity employment. The company's culture emphasizes innovation, collaboration, and making a significant impact through technology. This role is based in Bengaluru, India, offering the chance to work with Google's global teams while contributing to the company's hardware innovation initiatives.
Responsibilities For SoC RTL Design Engineer
- Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design
- Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks
- Work closely with the cross-functional team of Architecture, Verification, Design for Test, Physical Design, and Software teams to make design decisions
- Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc
Requirements For SoC RTL Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
- 3 years of experience in RTL coding using Verilog or Systemverilog language
- Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification
- English proficiency is a requirement
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