TPU Architect, Silicon

Google organizes the world's information and makes it universally accessible and useful, combining AI, Software, and Hardware to create helpful experiences.
Hardware
Mid-Level Software Engineer
Contact Company
3+ years of experience
AI · Hardware

Description For TPU Architect, Silicon

Google is seeking a TPU Architect to join their innovative hardware team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role combines cutting-edge machine learning, hardware architecture, and compiler optimization to push the boundaries of what's possible with Tensor Processing Units (TPUs).

As a TPU Architect, you'll be instrumental in analyzing and optimizing the performance and power efficiency of machine learning workloads on TPU architecture. You'll work with cross-functional teams to develop tools, flows, and dashboards for comprehensive performance analysis, while also proposing architectural improvements based on your findings.

The ideal candidate brings strong expertise in computer architecture, with specific knowledge of microarchitecture, cache hierarchy, pipelining, and memory subsystems. Experience with machine learning accelerators and algorithms is highly valued, as is familiarity with compiler optimization and tools like TensorFlow.

This position offers the opportunity to directly impact the future of Google's hardware experiences, working on technology that serves millions of users worldwide. You'll be part of a team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences, making computing faster, seamless, and more powerful.

Join Google's mission to organize the world's information and make it universally accessible and useful, while working on cutting-edge hardware solutions that push the boundaries of technology. This role offers the chance to work with industry-leading experts and shape the future of machine learning hardware acceleration.

Last updated 17 days ago

Responsibilities For TPU Architect, Silicon

  • Build up tools, flows, and dashboards for Tensor Processing Unit (TPU) power/performance analysis
  • Analyze important Machine Learning workloads, evaluate power and performance and propose architecture or compiler improvements
  • Analyze micro-architecture of the TPU, engage with the implementation team and propose power or performance optimization opportunities
  • Collaborate with cross-functional teams to improve the end to end workload analysis flows, including debugging and tracing

Requirements For TPU Architect, Silicon

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
  • 3 years of experience with computer architecture concepts, with microarchitecture, cache hierarchy, pipelining, and memory subsystems
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with computer architecture (preferred)
  • Experience with Machine Learning Accelerators (preferred)
  • Experience in Machine Learning algorithms (preferred)
  • Experience in architecting and optimizing compilers (preferred)
  • Knowledge of compiler flows (e.g., TensorFlow) (preferred)
  • English proficiency

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