Design Verification (DV) Engineer

Scientific trading firm specializing in algorithmic trading with sophisticated computing environments for research and development.
$120,000 - $200,000
Embedded
Mid-Level Software Engineer
In-Person
501 - 1,000 Employees
2+ years of experience
Finance

Description For Design Verification (DV) Engineer

Hudson River Trading (HRT) is seeking a Design Verification (DV) Engineer to join their Hardware team. The role focuses on creating high-performance compute engines using FPGA and ASIC technology for low-latency trading decisions. As a DV engineer, you'll be responsible for writing testbenches and building verification environments for complex HDL.

The position requires expertise in RTL functional verification, with a strong foundation in SystemVerilog and industry-standard frameworks like UVM. You'll be working in an innovative environment where you'll contribute to open-source projects and develop custom solutions ranging from bespoke circuits to machine learning accelerators.

HRT offers a unique culture that combines technical excellence with collaboration. The company brings together professionals from various disciplines, including mathematics, computer science, physics, and engineering. They value self-starters and embrace a culture of togetherness that extends beyond the office walls.

The role demands strong analytical skills and the ability to work in a fast-paced, real-time environment. You'll be part of a team that's actively working to rethink, redesign, and surpass the status quo in hardware verification. No financial experience is necessary, as HRT provides a sophisticated computing environment for research and development.

This is an excellent opportunity for someone who wants to be at the forefront of hardware verification in algorithmic trading, working with cutting-edge technology while being part of a diverse and inclusive team. HRT maintains offices globally and values varied perspectives, making it an ideal workplace for innovation and professional growth.

Last updated 2 months ago

Responsibilities For Design Verification (DV) Engineer

  • Creating testbenches and tests for hardware platform
  • Writing detailed verification plans
  • Root-cause RTL bugs analysis
  • Collaborating with designers for new projects and debugging
  • Managing test suites and continuous integration infrastructure
  • Developing and improving open-source and internal tools

Requirements For Design Verification (DV) Engineer

Python
Linux
  • Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
  • Experience with SystemVerilog and UVM frameworks
  • Experience with Python
  • Experience with code and functional coverage collection/analysis
  • Comfortable in Linux environment
  • Bachelor's degree in computer science, electrical engineering, or related field
  • Familiarity with Verilator and/or Cocotb preferred
  • C++ experience is a plus
  • Superb debug and analytical skills

Benefits For Design Verification (DV) Engineer

  • Equal Opportunity Employer
  • Collaborative Environment
  • Global Offices

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