Design Verification (DV) Engineer

Scientific trading firm bringing sophisticated computing and algorithmic approaches to financial products trading.
$175,000 - $225,000
Embedded
Mid-Level Software Engineer
In-Person
2+ years of experience
Finance

Description For Design Verification (DV) Engineer

Hudson River Trading (HRT) is seeking a Design Verification (DV) Engineer to join their Hardware team, which creates high-performance compute engines using FPGA and ASIC technology for low-latency trading decisions. The role focuses on building and maintaining sophisticated verification environments for complex hardware designs.

As a DV Engineer, you'll be part of an innovative team that's integral to HRT's trading success. You'll work with cutting-edge technology, creating testbenches and verification environments for complex HDL implementations. The team is actively involved in open-source projects like Slang, Verilator, and Cocotb, offering opportunities to contribute to the broader hardware verification community.

The position requires strong technical skills in hardware verification, including experience with SystemVerilog, UVM, and Python. You'll work in a fast-paced, real-time environment where your work directly impacts the company's trading infrastructure. The role offers competitive compensation and the opportunity to work with a diverse, collaborative team that values innovation and technical excellence.

HRT provides a unique culture that combines technical sophistication with a collaborative, friendly atmosphere. The company values diverse perspectives and creates an environment where great ideas are celebrated regardless of their source. Join a team that's pushing the boundaries of hardware verification while working on critical systems that drive modern financial markets.

Last updated 5 hours ago

Responsibilities For Design Verification (DV) Engineer

  • Creating testbenches and tests for hardware platform using hybrid open-source/proprietary environment
  • Writing detailed verification plans
  • Root-cause RTL bugs quickly
  • Collaborating with designers for rapid bringup of new projects and debugging
  • Managing test suites and continuous integration infrastructure
  • Developing and improving open-source and internal tools

Requirements For Design Verification (DV) Engineer

Python
Linux
  • Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
  • Experience with SystemVerilog and industry-standard frameworks such as UVM
  • Experience with code and functional coverage collection/analysis
  • Experience with Python
  • Comfortable in Linux environment
  • Bachelor's degree in computer science, electrical engineering, or related field
  • Superb debug and analytical skills
  • Familiarity with Verilator and/or Cocotb preferred
  • C++ experience is a plus

Benefits For Design Verification (DV) Engineer

Medical Insurance
  • Medical Insurance
  • Performance Bonus
  • Sign-on Bonus

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