FPGA/ASIC Design Engineer Intern
Description For FPGA/ASIC Design Engineer Intern
Hudson River Trading (HRT) is a leading scientific trading firm that combines cutting-edge technology with sophisticated algorithmic trading strategies. As an FPGA/ASIC Design Engineer Intern, you'll be at the forefront of high-performance hardware development, working with nanosecond-precision digital logic solutions.
The role offers a unique opportunity to work within HRT's advanced distributed trading system, where you'll be responsible for implementing mathematical models and performing real-time market data transformations. You'll be joining a collaborative team that values innovation and technical excellence, working with state-of-the-art FPGA and ASIC technologies.
HRT's culture celebrates diversity and promotes a collaborative environment where great ideas are valued regardless of their source. The company provides a sophisticated computing environment for research and development, making it an ideal place for those passionate about hardware engineering and financial technology.
The position offers competitive compensation, including a base salary range of $175,000-$250,000, plus sign-on and performance bonuses. You'll be part of a community of self-starters working at the cutting edge of automation across trading, business operations, and beyond. The company values work-life balance and fosters a culture of togetherness that extends beyond the office walls.
This internship is perfect for students who are naturally curious, enjoy problem-solving, and have a passion for hardware development. You'll have the opportunity to work with experienced professionals while contributing to real-world trading infrastructure that operates at the highest levels of performance and reliability.
Responsibilities For FPGA/ASIC Design Engineer Intern
- Work with cutting-edge technology within distributed trading system
- Identify efficient ways to perform on-the-fly transformations of market data
- Implement mathematical models
- Craft sophisticated digital logic solutions with nanosecond precision
Requirements For FPGA/ASIC Design Engineer Intern
- Full-time undergraduate student in computer science, computer engineering, electrical engineering, or related field
- Proficiency in SystemVerilog
- Understanding of FPGA and/or ASIC design flows and tools
- Excellent digital logic design, optimization, debugging, and problem solving skills
- Knowledge of computer architecture and network communication protocols
- Familiarity with C++ and/or Python
- Familiarity with Linux operating systems and system/processor performance
- Previous internship experience in digital logic design
Benefits For FPGA/ASIC Design Engineer Intern
- Sign-on bonus
- Performance bonus
- Medical benefits
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