Design Verification Engineer

Lightmatter is leading the revolution in AI data center infrastructure, inventing the world's first 3D-stacked photonics engine for extreme-scale data centers.
$200,000 - $250,000
Backend
Staff Software Engineer
Hybrid
51 - 100 Employees
12+ years of experience
AI · Enterprise SaaS

Description For Design Verification Engineer

Lightmatter is at the forefront of revolutionizing AI data center infrastructure with their groundbreaking 3D-stacked photonics engine, Passage™. This innovative technology enables connecting thousands to millions of processors at the speed of light, catering to the most advanced AI and HPC workloads.

As a Design Verification Engineer at Lightmatter, you'll be integral to a dynamic, interdisciplinary team. Your role involves close collaboration with digital design experts, using UVM testbench techniques for rigorous design verification. You'll work alongside photonic and analog designers, applying Real Number Modeling (RNM) and AMS verification methods to ensure design integrity.

Key responsibilities include developing comprehensive test plans, implementing UVM testbenches for subsystem and full-chip verification, and creating Real Number Models for photonics and analog circuits. You'll also contribute to the Golden Reference Model development and participate in emulation and formal verification processes.

This role offers a unique opportunity to enhance your skills across various areas, including UVM, AMS modeling, mixed-signal verification, and performance modeling. You'll be at the heart of innovation, working with brilliant scientists, engineers, and industry leaders to shape the future of computing with light.

Lightmatter recently raised $400 million in its Series D round, reaching a valuation of $4.4 billion. This funding will accelerate the development of data center photonics and support growth across all departments. If you're passionate about tackling complex challenges, making a significant impact, and becoming an expert in your craft, Lightmatter offers an exciting environment to push the boundaries of technology and contribute to groundbreaking advancements in AI infrastructure.

Last updated a month ago

Responsibilities For Design Verification Engineer

  • Engage collaboratively with teams specializing in digital, photonics, and analog design to develop comprehensive test plans
  • Design and implement UVM testbenches for both subsystem-level and full-chip verification
  • Develop Real Number Models (RNM) for photonics and analog circuits, conduct AMS verification in conjunction with UVM
  • Contribute significantly to the development of the Golden Reference Model (GRM) for design verification
  • Play an integral role in the execution of emulation and formal verification for DV purposes

Requirements For Design Verification Engineer

Python
  • Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience
  • 12 years of design verification and SystemVerilog experience
  • 2+ years of experience in python
  • Expertise in developing the UVM library
  • Experience with simulators such as Xcelium, ModelSim, Questa, or VCS

Benefits For Design Verification Engineer

Medical Insurance
Dental Insurance
Vision Insurance
401k
Commuter Benefits
Equity
  • Comprehensive Health Care Plan (Medical, Dental & Vision)
  • Retirement Savings Matching Program
  • Life Insurance (Basic, Voluntary & AD&D)
  • Generous Time Off (Vacation, Sick & Public Holidays)
  • Paid Family Leave
  • Short Term & Long Term Disability
  • Training & Development
  • Commuter Benefits
  • Flexible, hybrid workplace model
  • Stock Option Plan

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