Design Verification Engineer

Leading the revolution in AI data center infrastructure with the world's first 3D-stacked photonics engine, Passage™.
$150,000 - $250,000
Backend
Staff Software Engineer
Hybrid
101 - 500 Employees
12+ years of experience
AI · Enterprise SaaS

Description For Design Verification Engineer

Lightmatter is at the forefront of revolutionizing AI data center infrastructure with their groundbreaking 3D-stacked photonics engine, Passage™. Having recently secured $400 million in Series D funding at a $4.4 billion valuation, they're rapidly expanding their innovative work in data center photonics.

As a Design Verification Engineer, you'll be integral to a dynamic team working on cutting-edge technology that connects processors at the speed of light. The role combines expertise in UVM testbench techniques, Real Number Modeling (RNM), and AMS verification methods. You'll work closely with digital, photonic, and analog designers to ensure the integrity of their groundbreaking designs.

The position offers unique opportunities to enhance your skills across UVM, AMS modeling, mixed-signal verification, and formal verification. You'll be collaborating with brilliant scientists, engineers, and industry leaders while contributing to the future of computing with light. The role requires extensive experience in design verification and SystemVerilog, combined with Python expertise.

Lightmatter offers a comprehensive benefits package including health care, retirement savings, equity grants, and a flexible hybrid work model. The company's commitment to innovation, substantial funding, and revolutionary technology makes it an exciting opportunity for those passionate about making an impact in AI infrastructure and computing technology.

Join a team that's literally reinventing computing with light, working on technology that enables the next giant leaps in human progress. This role is perfect for someone who thrives in a fast-paced startup environment and wants to be at the forefront of transformative technology in AI and data center infrastructure.

Last updated 2 months ago

Responsibilities For Design Verification Engineer

  • Collaborate with digital, photonics, and analog design teams to develop test plans
  • Design and implement UVM testbenches for subsystem-level and full-chip verification
  • Develop Real Number Models (RNM) for photonics and analog circuits
  • Conduct AMS verification and ensure precise model representation
  • Contribute to Golden Reference Model (GRM) development
  • Execute emulation and formal verification

Requirements For Design Verification Engineer

Python
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
  • 12 years of design verification and SystemVerilog experience
  • 2+ years of experience in Python
  • Expertise in developing the UVM library
  • Experience with simulators like Xcelium, ModelSim, Questa, or VCS
  • Strong problem-solving and communication skills
  • Ability to work in a fast-paced startup environment

Benefits For Design Verification Engineer

Medical Insurance
Dental Insurance
Vision Insurance
401k
Parental Leave
Commuter Benefits
Equity
  • Comprehensive Health Care Plan (Medical, Dental & Vision)
  • Retirement Savings Matching Program
  • Life Insurance (Basic, Voluntary & AD&D)
  • Generous Time Off (Vacation, Sick & Public Holidays)
  • Paid Family Leave
  • Short Term & Long Term Disability
  • Training & Development
  • Commuter Benefits
  • Flexible, hybrid workplace model
  • Equity grants

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