Design Verification Engineer
Description For Design Verification Engineer
Lightmatter is at the forefront of revolutionizing AI data center infrastructure with their groundbreaking 3D-stacked photonics engine, Passage™. Having recently secured $400 million in Series D funding and reaching a $4.4 billion valuation, they're rapidly expanding their innovative work in data center photonics.
As a Design Verification Engineer, you'll be integral to a dynamic team working on cutting-edge technology that connects processors at the speed of light. You'll collaborate closely with digital design experts, photonic and analog designers, using advanced UVM testbench techniques and Real Number Modeling (RNM) for verification. The role demands expertise in SystemVerilog and Python, with opportunities to work on both subsystem-level and full-chip verification.
The position offers unique opportunities to enhance your skills across UVM, AMS modeling, mixed-signal verification, and formal verification. You'll work with brilliant scientists, engineers, and industry leaders, making a direct impact on the future of computing with light. The company offers comprehensive benefits, including health care, retirement matching, equity grants, and a flexible hybrid work model.
This role is perfect for someone who thrives on complex challenges, values making an impact, and wants to be part of revolutionizing computing technology. You'll be joining a company that's not just developing new technology, but fundamentally changing how data centers operate for AI and HPC workloads.
Responsibilities For Design Verification Engineer
- Engage collaboratively with teams specializing in digital, photonics, and analog design to develop comprehensive test plans
- Design and implement UVM testbenches for both subsystem-level and full-chip verification
- Develop Real Number Models (RNM) for photonics and analog circuits
- Contribute to the development of the Golden Reference Model (GRM) for design verification
- Execute emulation and formal verification for DV purposes
Requirements For Design Verification Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience
- 12 years of design verification and SystemVerilog experience
- 2+ years of experience in python
- Expertise in developing the UVM library
- Experience with simulators such as Xcelium, ModelSim, Questa, or VCS
Benefits For Design Verification Engineer
- Comprehensive Health Care Plan (Medical, Dental & Vision)
- Retirement Savings Matching Program
- Life Insurance (Basic, Voluntary & AD&D)
- Generous Time Off (Vacation, Sick & Public Holidays)
- Paid Family Leave
- Short Term & Long Term Disability
- Training & Development
- Commuter Benefits
- Flexible, hybrid workplace model
- Equity grants
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