ASIC, Design Verification Engineer
Description For ASIC, Design Verification Engineer
Meta, formerly Facebook Inc., is at the forefront of social technology innovation, expanding beyond traditional social media platforms to pioneer immersive experiences in augmented and virtual reality. As an ASIC Design Verification Engineer, you'll be instrumental in ensuring the quality and reliability of hardware systems that power Meta's next-generation technologies.
In this role, you'll work with cutting-edge hardware designs, developing and implementing comprehensive verification strategies for complex ASIC systems. You'll collaborate with cross-functional teams including Design, Model, Emulation, and Silicon validation teams, contributing to Meta's mission of building the future of social connection through hardware innovation.
The position offers an excellent opportunity to work with advanced technologies and methodologies, including SystemVerilog/UVM, while being part of Meta's journey in creating immersive social experiences. You'll be responsible for developing functional tests, driving verification closure, and ensuring the highest quality standards in hardware design.
Meta offers a competitive compensation package, including a base salary range of $191,902 to $234,520, plus bonus and equity opportunities. The company's commitment to pushing technological boundaries, combined with its global impact and strong engineering culture, makes this an exciting opportunity for experienced verification engineers looking to shape the future of social technology through hardware innovation.
Responsibilities For ASIC, Design Verification Engineer
- Develop functional tests based on verification test plan
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Define and implement IP/SoC verification plans, build verifications test benches to block IP/subsystem/SoC level verification
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams
Requirements For ASIC, Design Verification Engineer
- Bachelor's degree in Computer Science, Computer Software, Computer Engineering, Electrical and Computer Engineering, Applied Sciences, Mathematics, Physics, or related field
- 3 years of experience with System Verilog/UVM methodology or C/C++ based verification
- Track record of 'first-pass success' in ASIC development cycles
- Block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
- Experience with EDA tools and scripting (Python, TCL, Perl, Shell)
- Experience in architecting and implementing Design Verification infrastructure
Benefits For ASIC, Design Verification Engineer
- bonus
- equity
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