ASIC Engineer, Design

Meta builds technologies that help people connect, find communities, and grow businesses through social technology and immersive experiences.
Embedded
Principal Software Engineer
In-Person
5,000+ Employees
15+ years of experience
Enterprise SaaS

Description For ASIC Engineer, Design

Meta is seeking an experienced ASIC Design Engineer to join their Infrastructure organization. This role focuses on developing complex SoC and IP solutions for data center applications. The ideal candidate will bring 15+ years of silicon development experience and expertise in ASIC design, including architecture exploration, micro-architecture development, and RTL implementation.

The position offers an opportunity to work on cutting-edge technology at one of the world's leading tech companies. You'll be responsible for various aspects of ASIC design, from architecture exploration to power optimization, while collaborating with verification and implementation teams. The role requires strong technical skills in Verilog/System Verilog and experience with complex control and data path IPs.

Meta's mission involves connecting people and building communities through innovative technology. As an ASIC Engineer, you'll contribute to the infrastructure that powers Meta's various platforms and future initiatives in augmented and virtual reality. The company offers a diverse and inclusive work environment, with a strong commitment to equal employment opportunity and reasonable accommodations for all candidates.

The role is based in Bangalore, India, where you'll work with cross-functional teams to develop and implement sophisticated ASIC solutions. Your expertise in silicon development and track record of first-pass success will be crucial in driving the next generation of Meta's infrastructure forward. This is an excellent opportunity for experienced ASIC designers who want to impact billions of users while working on challenging technical problems at scale.

Last updated a day ago

Responsibilities For ASIC Engineer, Design

  • Architecture exploration
  • Micro-architecture development
  • RTL development using Verilog, System Verilog and HLS
  • Lint, CDC, Synthesis, & Power Optimization
  • Soft and hard IP identification, selection and integration
  • Collaboration with verification and emulation teams in test plan development and debug
  • Collaboration with implementation team to close the design on timing and power

Requirements For ASIC Engineer, Design

Python
  • 15+ years of silicon development experience
  • Track record of first-pass success in ASIC Development
  • Experience with Verilog or System Verilog
  • Experience in Micro-architecture and RTL development, SoC Micro-architecture, or Implementation
  • Experience working across multiple projects
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

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