ASIC Engineer, Design

Meta, a global technology leader known for connecting billions through platforms like Facebook, Instagram, and WhatsApp, is seeking an experienced ASIC Design Engineer to join their Infrastructure organization. This role presents an exciting opportunity to work on cutting-edge ASIC development in crucial fields such as machine learning, video transcoding, and network acceleration.

The position demands a highly skilled professional with extensive experience in SoC and IP development for data center applications. As an ASIC Design Engineer, you'll be responsible for various aspects of chip design, from architecture exploration to RTL development using Verilog and System Verilog. The role involves close collaboration with verification, emulation, and implementation teams to ensure successful design outcomes.

The ideal candidate brings 10+ years of experience in micro-architecture and RTL development, with a strong background in complex control and data path IPs or SoC design. Your expertise should span CPU architectures, Network-on-Chip (NOC), memory systems, and peripheral subsystems. Knowledge of synthesis, timing closure, and formal verification methodology is crucial for success in this role.

This position offers an attractive compensation package ranging from $173,000 to $249,000 annually, plus bonus, equity, and comprehensive benefits. Based in either Sunnyvale or Menlo Park, California, you'll be part of Meta's mission to push beyond traditional digital connections into immersive technologies like AR and VR.

Working at Meta means contributing to technologies that connect billions of people worldwide and helping shape the future of digital interaction. The company's commitment to innovation, coupled with its scale and resources, makes this an exceptional opportunity for an experienced ASIC engineer looking to make a significant impact in the field of hardware design for AI and data center applications.