ASIC Engineer, Design Verification
Description For ASIC Engineer, Design Verification
Meta is seeking an ASIC Design Verification Engineer to join their Infrastructure organization, focusing on developing innovative ASIC solutions for data center applications. This role combines traditional hardware engineering with modern technology needs, requiring expertise in SystemVerilog/UVM methodology and verification processes.
The position offers an opportunity to work with cutting-edge technology in Meta's data center infrastructure, where you'll be responsible for verification closure of design modules and sub-systems. You'll utilize various approaches including traditional simulation, Formal verification, and Emulation to ensure bug-free designs. The role requires collaboration with cross-functional teams including software, hardware, and ASIC Design teams.
As an ASIC Engineer, you'll be working on critical infrastructure components that power Meta's various platforms and services. The position offers competitive compensation ranging from $142,000 to $203,000 annually, plus bonus and equity opportunities. The role is based in either Sunnyvale, CA or Austin, TX, offering the chance to work with some of the industry's best talents.
The ideal candidate will bring 5+ years of experience in SystemVerilog/UVM methodology and verification, with a strong background in IP/sub-system verification. You'll need expertise in EDA tools and scripting languages like Python, TCL, and Perl. Meta's commitment to pushing technological boundaries means you'll be working on challenging projects that impact billions of users worldwide.
This role represents an excellent opportunity for experienced verification engineers looking to make an impact at scale, working on next-generation hardware infrastructure that powers Meta's social technology and immersive experiences. The position offers professional growth, competitive compensation, and the chance to work on cutting-edge technology in a collaborative environment.
Responsibilities For ASIC Engineer, Design Verification
- Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
- Develop functional tests based on verification test plan
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams
- Develop and drive continuous Design Verification improvements using the latest verification methodologies
Requirements For ASIC Engineer, Design Verification
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 5+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
- Track record of 'first-pass success' in ASIC development cycles
- 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell)
- Experience in architecting and implementing Design Verification infrastructure
Benefits For ASIC Engineer, Design Verification
- bonus
- equity
- benefits package available
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