ASIC Engineer, Design Verification

Meta is seeking an experienced ASIC Design Verification Engineer to join their Infrastructure organization. This role represents a unique opportunity to work with cutting-edge technology in data center applications, focusing on IP and System On Chip (SoC) development.

The position demands a seasoned professional with extensive experience in Design Verification, who will be responsible for comprehensive verification closure of design modules and sub-systems. The role encompasses everything from test-planning to UVM based testbench development and verification closure. The successful candidate will employ various approaches, including traditional simulation, Formal methods, and Emulation techniques to ensure bug-free design implementation.

Working at Meta offers the opportunity to collaborate with industry leaders and contribute to innovative ASIC solutions. The role involves significant interaction with full stack software, hardware, ASIC Design, Emulation, and Post-Silicon teams, all working together towards achieving first-pass silicon success. The position offers competitive compensation ranging from $212,000 to $291,000 annually, plus additional benefits including bonus and equity packages.

Key responsibilities include developing verification test benches, implementing functional tests, and driving verification to closure based on defined metrics. The ideal candidate will have 15+ years of experience in SystemVerilog/UVM methodology, strong debugging skills, and a proven track record of first-pass success in ASIC development cycles.

Meta's commitment to pushing technological boundaries, combined with its focus on connecting people and building communities, makes this an exciting opportunity for someone looking to make a significant impact in the field of ASIC design verification. The role offers the chance to work on cutting-edge projects while being part of a company that's shaping the future of digital connection and immersive technologies.