ASIC Engineer, Design Verification

Meta is seeking an ASIC Design Verification Engineer to join their Infrastructure organization. This role offers an exciting opportunity to work with industry leaders in developing innovative ASIC solutions for Meta's data center applications. As a Design Verification Engineer, you'll be responsible for comprehensive verification closure, from test-planning to UVM-based testbench development. You'll utilize traditional simulation methods alongside Formal and Emulation approaches to ensure bug-free design implementation.

The position offers extensive collaboration opportunities with full-stack software, hardware, ASIC Design, Emulation, and Post-Silicon teams, all working towards achieving first-pass silicon success. You'll be involved in developing functional tests, driving verification closure, debugging functional failures, and working closely with cross-functional teams.

The ideal candidate should have a strong educational background in Electronics Engineering or related fields, with experience in constrained-random verification, IP block verification, and EDA tools. Knowledge of computer architecture, CPU, GPU, or networking is essential. The role offers exposure to cutting-edge technology in Meta's infrastructure, working on projects that power billions of users' experiences across Meta's family of apps and future technologies.

This position is perfect for someone who wants to be at the forefront of hardware development in one of the world's leading tech companies, with opportunities to work on challenging problems and contribute to Meta's next generation of infrastructure solutions. The role combines technical depth with collaborative teamwork, making it ideal for engineers who want to grow their careers in hardware verification while working on impactful projects.