ASIC Engineer, Design Verification

Meta builds technologies that help people connect, find communities, and grow businesses through social technology and immersive experiences.
$212,000 - $291,000
Backend
Principal Software Engineer
In-Person
5,000+ Employees
15+ years of experience
AI · Enterprise SaaS

Description For ASIC Engineer, Design Verification

Meta is seeking an experienced ASIC Design Verification Engineer to join their Infrastructure organization. This role represents a unique opportunity to work with cutting-edge technology in data center applications, focusing on IP and System On Chip (SoC) development.

The position requires a seasoned professional with extensive experience in Design Verification, particularly in developing and implementing verification strategies for complex ASIC systems. As a Design Verification Engineer, you'll be working alongside industry experts in a dynamic environment, where innovation and technical excellence are paramount.

Your responsibilities will span the entire verification process, from test-planning to UVM-based testbench development and verification closure. The role involves working with both traditional simulation methods and advanced approaches like Formal and Emulation to ensure bug-free design implementation. You'll have the opportunity to collaborate with various teams, including full-stack software, hardware, ASIC Design, Emulation, and Post-Silicon teams, all working together toward achieving first-pass silicon success.

The ideal candidate will bring 15+ years of hands-on experience in SystemVerilog/UVM methodology and IP/sub-system verification. Your expertise should cover data-center applications, including Video, AI/ML, and Networking designs. Knowledge of specific areas such as Caches, Coherency, ROCE, and MMU is crucial.

Meta offers a competitive compensation package, including a base salary range of $212,000 to $291,000 per year, plus bonus and equity opportunities. The company provides a comprehensive benefits package and the chance to work on technologies that impact billions of users worldwide.

This role offers the unique opportunity to be part of Meta's mission to build the next evolution in social technology, moving beyond traditional 2D screens toward immersive experiences in augmented and virtual reality. You'll be contributing to groundbreaking innovations that will shape the future of digital connection and communication.

Last updated a month ago

Responsibilities For ASIC Engineer, Design Verification

  • Define and implement IP/SoC verification plans
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics
  • Debug, root-cause and resolve functional failures in the design
  • Collaborate with cross-functional teams
  • Develop and drive continuous Design Verification improvements

Requirements For ASIC Engineer, Design Verification

Python
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • Track record of 'first-pass success' in ASIC development cycles
  • 15+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
  • 15+ years experience in IP/sub-system and/or SoC level verification
  • Experience with Design verification of Data-center applications
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell)
  • Experience in architecting and implementing Design Verification infrastructure

Benefits For ASIC Engineer, Design Verification

Medical Insurance
Equity
  • bonus
  • equity
  • benefits

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