ASIC Engineer, Design Verification

Meta builds technologies that help people connect, find communities, and grow businesses through social technology and immersive experiences.
$212,000 - $291,000
Embedded
Principal Software Engineer
In-Person
5,000+ Employees
15+ years of experience
AI · Enterprise SaaS

Description For ASIC Engineer, Design Verification

Meta is seeking an experienced ASIC Design Verification Engineer to join their Infrastructure organization. This role focuses on building IP and System On Chip (SoC) solutions for data center applications. As a Design Verification Engineer, you'll be part of an innovative team working with industry leaders to develop cutting-edge ASIC solutions. The position involves comprehensive verification responsibilities, from test-planning to UVM-based testbench development and verification closure. You'll utilize various approaches including traditional simulation, Formal methods, and Emulation to ensure bug-free designs. The role offers extensive opportunities to collaborate with full-stack software, hardware, ASIC Design, Emulation, and Post-Silicon teams. Meta's commitment to pushing technological boundaries, combined with their focus on connecting billions of people worldwide through their platforms, makes this an exciting opportunity for experienced verification engineers looking to make a significant impact in data center technology. The position offers competitive compensation, including base salary, bonus, equity, and comprehensive benefits, reflecting Meta's investment in top talent.

Last updated 17 hours ago

Responsibilities For ASIC Engineer, Design Verification

  • Define and implement IP/SoC verification plans, build verification test benches
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics
  • Debug, root-cause and resolve functional failures in the design
  • Collaborate with cross-functional teams
  • Develop and drive continuous Design Verification improvements

Requirements For ASIC Engineer, Design Verification

Python
Linux
  • Bachelor's degree in Computer Science, Computer Engineering, or relevant technical field
  • 15+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++
  • 15+ years experience in IP/sub-system and/or SoC level verification
  • Experience with Design verification of Data-center applications
  • Experience in Caches, Coherency, ROCE, MMU
  • Experience in EDA tools and scripting
  • Experience in architecting and implementing Design Verification infrastructure

Benefits For ASIC Engineer, Design Verification

Medical Insurance
Dental Insurance
Vision Insurance
  • Bonus
  • Equity
  • Comprehensive benefits package

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