ASIC Engineer, Methodology

Meta is seeking an experienced ASIC Methodology Engineer to join their Infrastructure organization, focusing on design integrity and signoff methodology development. This role is crucial for developing and implementing timing signoff flows for complex disaggregated ASICs used in data center applications.

The position offers an opportunity to work with cutting-edge technology at one of the world's leading tech companies. As an ASIC Methodology Engineer, you'll be responsible for collaborating with vendor partners and foundries, developing internal timing signoff methods, and ensuring design integrity for Meta's System on Chip (SoC) implementations.

The ideal candidate will bring 12+ years of experience in STA, modeling, and signoff methodology development. You'll work with advanced EDA tools and contribute to the development of robust timing signoff automation. The role requires expertise in library characterization, process technology evaluation, and test chip development across multiple nodes/foundries.

This is an excellent opportunity for someone who wants to impact the future of Meta's hardware infrastructure. You'll be working on challenging technical problems while collaborating with cross-functional teams. The position offers competitive compensation ($212,000-$291,000/year) plus bonus, equity, and comprehensive benefits.

The role is based in either Sunnyvale, CA or Austin, TX, and offers the chance to work on projects that will directly influence Meta's next generation of hardware solutions. You'll be part of a team that's pushing the boundaries of what's possible in ASIC design and methodology, contributing to Meta's mission of building technologies that help people connect and communicate.

If you're passionate about hardware engineering, have deep expertise in ASIC methodology, and want to work on projects that will shape the future of social technology infrastructure, this role presents an exciting opportunity to advance your career while making a significant impact.