ASIC Engineer, Physical Design

Meta is seeking an experienced ASIC Physical Design Engineer to join their Infrastructure organization. This role focuses on building efficient System on Chip (SoC) and IP for data center applications. The ideal candidate will have extensive experience in backend implementation from Netlist to GDSII in low power and high-performance designs.

The position requires a deep understanding of physical design implementation, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, and static timing analysis. You'll work with cutting-edge technology nodes and be responsible for delivering end-to-end IP or integration of ASIC/SoC designs.

At Meta, you'll be part of a team that's pushing the boundaries of technology, working on projects that impact billions of users worldwide. The company is moving beyond traditional 2D screens toward immersive experiences like augmented and virtual reality, making this an exciting time to join the hardware team.

The role offers the opportunity to work with state-of-the-art EDA tools and advanced process technologies, while collaborating with cross-functional teams and industry vendors. You'll be instrumental in driving design modifications, resolving complex technical challenges, and implementing solutions that optimize both performance and power efficiency.

This position is perfect for someone who combines technical expertise with strong communication skills, as you'll be interfacing with various teams and stakeholders. The role offers the chance to work on large-scale SOC designs and contribute to Meta's next generation of hardware infrastructure.