ASIC Engineer, Physical Design
Description For ASIC Engineer, Physical Design
Meta is seeking an experienced ASIC Physical Design Engineer to join their Infrastructure organization. This role focuses on developing and implementing physical designs for high-performance System on Chip (SoC) and IP solutions for data center applications. The position requires expertise in backend implementation from Netlist to GDSII, with emphasis on low power and high-performance designs.
The ideal candidate will have extensive experience with advanced technology nodes and be proficient in various aspects of physical design, including synthesis, floorplanning, place and route, and timing analysis. They will work closely with RTL design teams to optimize designs and resolve technical challenges, while also collaborating with tool vendors to improve processes and workflows.
This role offers an opportunity to work on cutting-edge technology at Meta, contributing to the development of infrastructure that powers social connectivity and immersive experiences. The position comes with competitive compensation, including a base salary range of $173,000 to $249,000, plus bonus and equity opportunities.
Meta's commitment to building the next evolution in social technology makes this an exciting opportunity for experienced professionals who want to shape the future of digital connectivity. The role combines technical expertise with collaborative teamwork, offering a chance to work on large-scale, complex systems that impact billions of users worldwide.
Responsibilities For ASIC Engineer, Physical Design
- Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs
- Resolve design and flow issues related to the physical design
- Deliver physical design of an end-to-end IP or integration of ASIC/SoC design
- Define and implement schemes to improve performance and power
- Work with RTL design team on partition architecture
- Interface with RTL design team to resolve congestion/timing issues
- Use EDA tool-based programming and scripting techniques
- Interact with tool vendors for fixes and flow improvements
Requirements For ASIC Engineer, Physical Design
- Experience in physical design and timing closure
- Bachelor's degree in Computer Science, Computer Engineering, or relevant technical field
- Knowledge of RTL2GDSII flow and design tape-outs in 5nm or below process technologies
- Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Redhawk/Voltus, or Calibre
- Hands-on experience in SoC floor planning
- Knowledge of geometry/process/device technology implications
- Experience with large SOC designs (>100M gates) with frequencies over 1GHZ
- 10+ years of experience in interpersonal teamwork
- Programming/scripting skills: TCL, Python, Perl or Shell
Benefits For ASIC Engineer, Physical Design
- bonus
- equity
- benefits
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