ASIC Engineer, Physical Design
Description For ASIC Engineer, Physical Design
Meta is seeking an experienced ASIC Physical Design Engineer to join their Infrastructure organization. This role presents an exciting opportunity to work on cutting-edge technology in data center applications, focusing on System on Chip (SoC) and IP development.
The position requires expertise in backend implementation from Netlist to GDSII, with a focus on low power and high-performance designs. You'll be working with advanced technology nodes (7nm and below), handling complex physical design implementations including physical-aware logic synthesis, floorplan, place and route, and clock tree synthesis.
As an ASIC Engineer at Meta, you'll be part of a team that's pushing the boundaries of AI Infrastructure and Hardware Engineering. You'll collaborate with RTL design teams, interface with tool vendors, and have the opportunity to influence tool development and flow improvements. The role combines technical expertise with cross-functional collaboration, requiring both deep technical knowledge and strong communication skills.
The compensation package is competitive, ranging from $114,000 to $166,000 annually, plus bonus and equity opportunities. Meta offers comprehensive benefits and the chance to work on technology that impacts billions of users globally.
This role is perfect for someone who has a strong background in physical design, enjoys solving complex technical challenges, and wants to contribute to the next generation of data center infrastructure. You'll be working in either the San Francisco Bay Area or Austin, where you'll have access to Meta's world-class facilities and collaborate with some of the industry's best minds.
The position offers growth opportunities through exposure to cutting-edge technology and the chance to work on projects that directly impact Meta's infrastructure. You'll be part of a team that's driving innovation in ASIC design, with the opportunity to work on advanced packaging technologies and 3D-IC implementations.
If you're passionate about hardware engineering, have a strong background in physical design, and want to be part of shaping the future of digital infrastructure, this role offers the perfect blend of challenge, innovation, and impact.
Responsibilities For ASIC Engineer, Physical Design
- Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs
- Resolve design and flow issues related to the physical design
- Deliver physical design of an end-to-end IP or integration of ASIC/SoC design
- Define and implement schemes to improve performance and power
- Work with RTL design team on partition architecture
- Interface with RTL design team for design modifications
- Use EDA tool-based programming and scripting
- Interact with tool vendors for tool fixes and flow improvements
Requirements For ASIC Engineer, Physical Design
- Bachelor's degree in Computer Science, Computer Engineering, or relevant technical field
- Experience in physical design and timing closure
- 3+ years of experience in interpersonal teamwork and communication
- Knowledge of RTL2GDSII flow and design tape-outs in 7nm or below
- Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime
- Hands-on experience in floor planning, place & route
- Knowledge of geometry/process/device technology
- Programming/scripting skills: TCL, Python, Perl or Shell
Benefits For ASIC Engineer, Physical Design
- bonus
- equity
- benefits
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