ASIC Engineer, Power

Meta is hiring ASIC Power Engineers within our Infrastructure organization to work on power/performance optimizations from SOC Architecture to System level. We are looking for individuals with experience in power architecture definition and power management for large complex disaggregated ASICs, with exposure to power modeling, developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center applications.

Responsibilities:

• Work with Architecture and Design teams to assess power/performance tradeoffs
• Define power specifications at system and module level
• Develop power modeling infrastructure in Python/C++
• Work with or develop architectural simulators for performance and power modeling
• Build power estimation flows at various levels of abstraction
• Optimize design for low-power with system level concepts
• Power characterization on silicon and debug power issues
• Partner with vendors for low-power requirements and EDA tool selection
• Collaborate with internal teams for power flows, optimization, and estimation

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, or equivalent
• 15+ years of experience with power architecture specification, modeling, and design
• Experience with EDA tools and scripting languages (Python, Tcl)

Preferred Qualifications:

• Experience with architectural performance and power models at SoC and system level
• Knowledge of low-power design techniques
• Experience architecting systems for various design scales
• Post-silicon bring-up and debug experience
• Understanding of ASIC design process and power concepts
• Experience managing multiple design releases and cross-functional collaboration
• RTL design experience using SystemVerilog or other HDL

Meta offers competitive compensation, including bonus, equity, and benefits. Join us in shaping the future of social technology beyond 2D screens towards immersive experiences like AR and VR.