ASIC Implementation Engineer - Synthesis
Description For ASIC Implementation Engineer - Synthesis
Meta is seeking an experienced ASIC Implementation Engineer to join their Infrastructure organization, focusing on front-end implementation from RTL to netlist. This role combines technical expertise in ASIC design with strategic problem-solving skills.
The position involves working with cutting-edge technology in Meta's infrastructure, specifically designing and optimizing System on Chip (SoC) and IP for data center applications. As an ASIC Implementation Engineer, you'll be responsible for running Logic/Physical Synthesis, debugging complex timing issues, performing power estimations, and ensuring quality through various verification processes.
The ideal candidate will bring 5+ years of experience in Front End Synthesis & Integration Engineering, with a strong background in RTL design and optimization. You'll need expertise in SystemVerilog or other HDL languages, and familiarity with various EDA tools and scripting languages like Python and TCL.
This role offers an exciting opportunity to work at the intersection of hardware and software, contributing to Meta's next-generation infrastructure. You'll collaborate with cross-functional teams, including Design Engineers, DV Engineers, and Physical Design Engineers, making this position perfect for someone who enjoys both technical challenges and team collaboration.
The compensation package is highly competitive, ranging from $142,000 to $203,000 annually, plus bonus and equity opportunities. Working at Meta means being part of a company that's pushing the boundaries of social technology, including ventures into augmented and virtual reality.
The position is based in the San Francisco Bay Area and offers the chance to work on projects that will help shape the future of digital connection. Meta provides a comprehensive benefits package and maintains a strong commitment to diversity, equality, and inclusion in their hiring practices.
If you're passionate about ASIC design, have a strong technical background, and want to contribute to building the next evolution in social technology infrastructure, this role presents an excellent opportunity to advance your career while working on impactful projects at a global scale.
Responsibilities For ASIC Implementation Engineer - Synthesis
- Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power
- Debug timing/area/congestion issues and work with RTL & Physical designers
- Perform Power Estimation at RTL and Gate Level
- Run Formal Verification checks between RTL and Gate level netlist
- Perform RTL Lint and work with Designers to create waivers
- Perform RTL DFT Analysis and improve DFT coverage
- Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA
- Analyze inter-block timing and develop IO budgets
- Develop Automation scripts and Methodology for FE-tools
- Work with Design, DV, and Emulation Engineers
- Interact with Physical Design Engineers
Requirements For ASIC Implementation Engineer - Synthesis
- Bachelor's degree in Computer Science, Computer Engineering, or relevant technical field
- 5+ Years of experience as a Front End Synthesis & Integration Engineer
- Experience with RTL Synthesis and design optimization
- Knowledge of front-end and back-end ASIC tools
- Experience with RTL design using SystemVerilog or other HDL
- Experience managing multiple design releases
- Experience with communicating across functional internal teams and vendors
Benefits For ASIC Implementation Engineer - Synthesis
- bonus
- equity
- benefits
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