Design Verification Engineer (University Grad)

Meta builds technologies that help people connect, find communities, and grow businesses through social technology and immersive experiences.
$114,000 - $133,000
Embedded
Entry-Level Software Engineer
In-Person
5,000+ Employees
AR/VR

Description For Design Verification Engineer (University Grad)

Meta's Reality Labs (RL) is seeking a Design Verification Engineer to join their innovative team focused on Augmented Reality (AR) technology. This role is perfect for university graduates who want to work on cutting-edge custom silicon development for AR devices. As part of the RL Silicon team, you'll be instrumental in pushing the boundaries of computer vision, machine learning, mixed reality, and graphics.

The position offers an exciting opportunity to work with world-class researchers and engineers, using your digital design and verification skills to validate new core IP and SoC implementations. You'll be deeply involved in creating test bench requirements and test cases, working directly with researchers and architects to ensure the highest quality standards.

The role combines technical expertise in verification methodologies like UVM with programming skills in languages such as System Verilog, C++, and Python. You'll be responsible for developing verification plans, tracking metrics, and collaborating with cross-functional teams to resolve design challenges.

Meta offers a competitive compensation package, including a base salary range of $114,000-$133,000, plus bonus and equity opportunities. The company's commitment to pushing technological boundaries in AR/VR makes this an ideal position for someone passionate about shaping the future of human-computer interaction.

Working at Meta's Reality Labs means being part of a team that's looking at the entire technology stack, from transistor-level implementations to high-level algorithms. This comprehensive approach provides an unique opportunity to make significant contributions to the next generation of AR devices that will seamlessly blend our real and virtual worlds.

Last updated 20 hours ago

Responsibilities For Design Verification Engineer (University Grad)

  • Work with researchers and architects defining verification plans for core IP or SoCs
  • Define and track detailed test plans for different modules and top levels
  • Drive Design Verification to closure based on defined verification metrics
  • Debug, root-cause and resolve functional failures in the design
  • Collaborate with cross-functional teams
  • Develop and drive continuous Design Verification improvements

Requirements For Design Verification Engineer (University Grad)

Python
  • Bachelor's degree in Computer Science, Computer Engineering, or relevant technical field
  • Experience in languages such as System Verilog, C, C++
  • Experience with verification methodologies like UVM
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell)
  • Experience analyzing complex problems
  • Must obtain work authorization
  • Interpersonal experience: cross-group and cross collaboration

Benefits For Design Verification Engineer (University Grad)

Medical Insurance
Dental Insurance
Vision Insurance
  • bonus
  • equity
  • benefits

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