Digital Design Engineer

Meta's Reality Labs (RL) is seeking Digital Design Engineers to join their Machine Learning ASIC Design and µArchitecture team. The role focuses on developing and optimizing low power machine learning accelerators and state-of-the-art SoCs for Virtual Reality (VR) and Augmented Reality (AR) applications.

Responsibilities include:

• Contributing to ASIC digital µArchitecture and design for low-power machine learning hardware accelerators
• Assisting with performance/power analysis and meeting power and performance targets
• Working with architects to map Machine learning algorithms on hardware
• Supporting hand-off and integration of blocks into larger SOC environments
• Collaborating across disciplines to brainstorm ideas and build new methodologies

Requirements:

• 5+ years of experience as a Hardware Design Engineer for production silicon shipped in volume
• Experience in digital design µArchitecture and RTL coding
• Experience in Machine Learning IPs Silicon development
• Proficiency in at least one procedural programming language (C, C++, Python, etc.)
• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field

Preferred qualifications include experience in SoC integration, ASIC architecture, knowledge of Physical Design and Low power implementation, and experience with Machine learning models, algorithms, or accelerator architecture.

This role offers an opportunity to work on cutting-edge technology in the AR/VR space, contributing to Meta's vision of mixing real and virtual worlds throughout the day. The position is based in Sunnyvale, CA, and offers competitive compensation ranging from $136,000 to $203,000 per year, plus bonus, equity, and benefits.