Meta Reality Labs is seeking an experienced FPGA Design Engineer to join their Metaverse Prototyping Team, working on cutting-edge hardware development for the next evolution of social technology. This role offers an exciting opportunity to work at the intersection of hardware engineering and virtual/augmented reality, developing solutions that will shape the future of human connection.
The position requires a seasoned professional with 8+ years of FPGA design experience, who will be responsible for driving RTL development, testing, and implementation of FPGA-based solutions. You'll work in a multidisciplinary environment, collaborating with teams across Hardware Engineering, Research and Development, and Industrial Design to bring new ideas to life through high-fidelity prototypes.
Key responsibilities include developing and testing RTL for FPGA platforms, partnering with various teams to solve complex technical challenges, and supporting algorithm analysis and verification. You'll also be involved in developing system-level specifications and managing multiple concurrent projects.
The ideal candidate will have extensive experience with HDL simulators, Verilog/SystemVerilog, and various communication protocols. Knowledge of streaming video protocols, cameras, and optical systems is a plus. The role offers competitive compensation ranging from $170,000 to $240,000 annually, plus bonus and equity opportunities.
At Meta, you'll be part of a team that's pushing the boundaries of what's possible in AR/VR technology, working on projects that directly impact the development of the Metaverse. The company offers comprehensive benefits and maintains a strong commitment to diversity, equality, and inclusion.
This is an excellent opportunity for an experienced FPGA engineer who wants to work on groundbreaking technology while collaborating with some of the best minds in the industry. You'll be instrumental in developing the hardware infrastructure that will power the next generation of social interaction and digital experiences.