Design Verification Engineer

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world.
$98,300 - $193,200
Backend
Senior Software Engineer
Hybrid
5,000+ Employees
5+ years of experience
Enterprise SaaS · Gaming

Description For Design Verification Engineer

Microsoft's Semi-custom and Central IP Silicon (SCIPS) team is seeking a passionate Design Verification Engineer to join their innovative hardware engineering team. This role offers an exciting opportunity to work on critical IPs for various Microsoft products, from Xbox to Azure cloud servers. The position involves developing systematic methods to verify hardware designs and detect vulnerabilities.

The role combines technical expertise in hardware verification with the chance to impact Microsoft's diverse product portfolio. You'll work with cross-functional teams, using advanced technologies and methodologies including SystemVerilog, UVM, and various scripting languages. The position offers competitive compensation, comprehensive benefits, and the opportunity to work in a hybrid environment.

As a Design Verification Engineer, you'll be responsible for creating verification environments, developing test cases, and ensuring the quality of hardware designs. The role requires strong technical skills in hardware verification, programming, and debugging, along with the ability to collaborate effectively with design and architecture teams.

Microsoft offers an inclusive work environment, competitive compensation ($98,300 - $193,200), and comprehensive benefits including healthcare, educational resources, and parental leave. This is an excellent opportunity for experienced verification engineers looking to work on cutting-edge technology products at a global scale.

Last updated a day ago

Responsibilities For Design Verification Engineer

  • Plan verification of complex design IP with architecture and design engineers
  • Create constrained-random verification environments using SystemVerilog and UVM
  • Develop tests using UVM or C/C++
  • Analyse and debug test failures
  • Identify and write functional coverage for stimulus and corner cases
  • Close coverage to meet tape out requirements

Requirements For Design Verification Engineer

Python
Ruby
  • 5+ years of related technical engineering experience or Bachelor's with 2+ years experience or Master's with 1+ year experience
  • 3+ years experience in developing test plans, simulation environments, and debugging
  • Proficient in SystemVerilog, C/C++, and scripting languages
  • Must pass Microsoft Cloud Background Check
  • Solid understanding of chip and computer architecture
  • Experience with secure hardware design for embedded systems
  • Experience with hardware emulation or FPGAs

Benefits For Design Verification Engineer

Medical Insurance
Education Budget
Parental Leave
Mental Health Assistance
  • Industry leading healthcare
  • Educational resources
  • Discounts on products and services
  • Savings and investments
  • Maternity and paternity leave
  • Generous time away
  • Giving programs
  • Opportunities to network and connect

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