Design Verification Engineer II

A highly innovative company that collaborates across disciplines to produce cutting edge technology.
$98,300 - $193,200
Hardware
Mid-Level Software Engineer
Hybrid
5,000+ Employees
5+ years of experience
AI

Description For Design Verification Engineer II

Microsoft's AI Silicon Engineering (AISiE) SoC Design Verification team is seeking a Design Verification Engineer II to work on cutting-edge AI accelerators. The role involves collaborating with cross-discipline teams to develop verification environments and test cases for Microsoft's latest AI accelerators. The position is part of a team responsible for delivering custom IP and SoC designs for high-performance AI operations. The ideal candidate should be passionate about developing systematic methods to detect hardware/software vulnerabilities and will work in a culture that values respect, integrity, and accountability. This role offers competitive compensation, comprehensive benefits, and the opportunity to work on innovative AI hardware solutions at one of the world's leading technology companies. The position combines technical expertise in hardware verification with the chance to impact the future of AI acceleration technology.

Last updated 12 days ago

Responsibilities For Design Verification Engineer II

  • Creation of verification environments
  • Pre-silicon functional verification at block, chip and system level
  • Functional and performance modeling
  • Post silicon validation
  • Embody Microsoft's Culture and Values

Requirements For Design Verification Engineer II

  • 5+ years of related technical engineering experience OR Bachelor's degree in EE/CE/CS with 2+ years experience OR Master's degree with 1+ year experience
  • Must pass Microsoft Cloud Background Check
  • Must meet export control regulations requirements
  • Knowledge of verification principles, testbenches, System Verilog, UVM
  • Experience with hardware design for embedded systems
  • Firmware development experience
  • Experience with hardware emulation or FPGAs
  • Effective communication skills

Benefits For Design Verification Engineer II

Medical Insurance
Education Budget
Parental Leave
  • Industry leading healthcare
  • Educational resources
  • Discounts on products and services
  • Savings and investments
  • Maternity and paternity leave
  • Generous time away
  • Giving programs
  • Opportunities to network and connect

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