Principal Circuit Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions.

As Microsoft's cloud business continues to grow, the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Semi and Custom IP team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware.

We are looking for a Principal Circuit Design Engineer to design and build customer-focused solutions, discover insights and utilize industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

Responsibilities:

• Collaborate with SoC designers to develop Memory SRAM and Register file solutions to difficult PPA challenges
• Work with internal and external process technology teams to understand and exploit advanced process DTCO knobs
• Serve as technical lead to a team of circuit and mask layout engineers
• Devise methodologies for statistical analysis and timing/power/EMIR characterization
• Work alongside IP and SoC program management to develop milestone schedules and ensure proper delivery
• Direct IP collateral quality assurance checking
• Develop IP and post-silicon characterization plans for inclusion on advanced process technology testchips
• Develop scripting automation for flows

Required Qualifications:

• 9+ years of related technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
• 6+ years of experience in SRAM OR Register file design

Preferred Qualifications:

• Understanding of SRAM write and read assist techniques
• Deep understanding of industry trends in process and system-level technology
• Expertise in yield and reliability
• Experience in providing technical guidance to other engineers and multitasking across multiple SoC programs
• Ability to concisely communicate design value propositions and risks
• Excellent debug skills
• 6+ years of experience in timing, power, EMIR characterization

Benefits include industry-leading healthcare, educational resources, discounts on products and services, savings and investments, maternity and paternity leave, generous time away, giving programs, and opportunities to network and connect.