Principal Design Verification Engineer

Microsoft builds custom silicon for systems ranging from Xbox to Azure cloud servers, clients, and augmented reality.
Embedded
Principal Software Engineer
Hybrid
5,000+ Employees
15+ years of experience
AI · Enterprise SaaS

Description For Principal Design Verification Engineer

Microsoft's Silicon team is seeking a Principal Design Verification Engineer to join their Artificial Intelligence System on Chip (AISoC) team. This role represents a unique opportunity to work at the forefront of custom silicon development, spanning from consumer products like Xbox to high-performance Azure cloud servers.

The ideal candidate will bring 15+ years of design verification experience, with a proven track record in delivering complex CPU or SoC IP's. You'll be working in a cutting-edge technical environment, leading verification efforts for sophisticated hardware systems that power Microsoft's AI initiatives.

The role demands expertise in UVM or C++, RTL debugging, and simulation environments. You'll be responsible for developing verification strategies, running simulations, and ensuring quality through coverage-based techniques. The position offers the chance to innovate in verification methodologies while mentoring others in the team.

Working at Microsoft means joining a company that values diversity, inclusion, and personal growth. The benefits package includes industry-leading healthcare, educational resources, parental leave, and various other perks. The hybrid work environment (up to 50% work from home) offers flexibility while maintaining collaborative opportunities.

This is an exceptional opportunity for a seasoned verification engineer who wants to make a significant impact in the AI hardware space while working with cutting-edge technology. You'll be part of a team that's pushing the boundaries of what's possible in custom silicon design, contributing to Microsoft's mission of empowering every person and organization on the planet to achieve more.

Last updated a month ago

Responsibilities For Principal Design Verification Engineer

  • Own or lead verification of complex flows at the SOC, subsystem, or IP levels
  • Define verification strategies and test plans through partner team interaction
  • Develop verification environments and run/debug simulations
  • Apply random-stimulus and coverage-based techniques
  • Innovate to improve verification efficiency
  • Coach and mentor others in areas of expertise
  • Plan verification of complex design IP/SoC
  • Demonstrate Microsoft core values

Requirements For Principal Design Verification Engineer

Python
  • 15+ years of experience in design verification with proven track record of delivering complex CPU or SoC IP's
  • Experience with verification for multiple product cycles using UVM or C++
  • Background in debugging RTL (Verilog) designs and simulation/emulation environments
  • Scripting knowledge in Python or Perl
  • Hands on experience in Formal property verification (desired)
  • Knowledge in high-speed protocols like DDR/HBM, PCIe, Ethernet (desired)
  • Experience of working on AI/ML SoCs (desired)

Benefits For Principal Design Verification Engineer

Medical Insurance
Education Budget
Parental Leave
  • Industry leading healthcare
  • Educational resources
  • Discounts on products and services
  • Savings and investments
  • Maternity and paternity leave
  • Generous time away
  • Giving programs
  • Opportunities to network and connect

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