Principal Design Verification Engineer

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world.
$137,600 - $294,000
Embedded
Principal Software Engineer
Hybrid
5,000+ Employees
9+ years of experience
AI

Description For Principal Design Verification Engineer

Microsoft's Artificial Intelligence Silicon Engineering (AISiE) team is seeking a Principal Design Verification Engineer to work on cutting-edge AI accelerators. This role involves collaborating with cross-discipline teams including systems, firmware, architecture, design, validation, and product engineering. The position requires extensive experience in silicon verification, chip architecture, and programming languages. The successful candidate will be responsible for creating verification environments, conducting pre-silicon functional verification, and post-silicon validation. Microsoft offers a comprehensive benefits package and promotes a culture of inclusion and innovation. The role provides an opportunity to work on advanced AI hardware technology while contributing to Microsoft's mission of empowering every person and organization on the planet to achieve more. The position offers competitive compensation with a base salary range of $137,600 - $294,000, depending on location, along with additional benefits and opportunities for professional growth.

Last updated 3 hours ago

Responsibilities For Principal Design Verification Engineer

  • Creation of verification environments and tests
  • Pre-silicon functional verification at the block, chip and system level
  • Reference modeling and post-silicon validation
  • Work with cross-discipline teams to develop environment and test cases
  • Embody Microsoft Culture and Values

Requirements For Principal Design Verification Engineer

Python
Linux
  • 9+ years of related technical engineering experience or equivalent combination of education and experience
  • Experience in creating simulation environments, developing tests, and debugging for multiple silicon IPs or systems
  • 5+ years industry experience of chip and/or computer architecture
  • 5+ years industry experience in Verilog or VHDL, C/C++, and scripting languages
  • Must pass Microsoft Cloud Background Check
  • Must meet export control regulations requirements

Benefits For Principal Design Verification Engineer

Medical Insurance
Education Budget
Parental Leave
  • Industry leading healthcare
  • Educational resources
  • Discounts on products and services
  • Savings and investments
  • Maternity and paternity leave
  • Generous time away
  • Giving programs
  • Opportunities to network and connect

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