Principal Design Verification Engineer

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world.
$137,600 - $294,000
Embedded
Principal Software Engineer
Hybrid
9+ years of experience
AI

Description For Principal Design Verification Engineer

Microsoft's Artificial Intelligence Silicon Engineering (AISiE) team is seeking a Principal Design Verification Engineer to join their innovative System on Chip (SoC) Design Verification team. This role focuses on developing cutting-edge AI accelerators, working across multiple disciplines including systems, firmware, architecture, design, validation, and product engineering. The position requires extensive experience in silicon verification, chip architecture, and programming languages. The role offers competitive compensation ranging from $137,600 to $294,000 depending on location, with higher ranges for San Francisco and New York City areas. The position features a hybrid work arrangement with up to 50% work from home opportunity. Microsoft provides comprehensive benefits including healthcare, educational resources, and parental leave. The ideal candidate will have 9+ years of experience in technical engineering with strong skills in verification environments, test development, and debugging for silicon IPs. This role represents an opportunity to work at the forefront of AI hardware development while contributing to Microsoft's mission of empowering every person and organization on the planet to achieve more.

Last updated 25 days ago

Responsibilities For Principal Design Verification Engineer

  • Creation of verification environments and tests
  • Pre-silicon functional verification at the block, chip and system level
  • Reference modeling and post-silicon validation
  • Work with cross-discipline teams to develop environment and test cases
  • Embody Microsoft Culture and Values

Requirements For Principal Design Verification Engineer

Python
Ruby
  • 9+ years of related technical engineering experience or equivalent combination of education and experience
  • Experience in creating simulation environments, developing tests, and debugging for multiple silicon IPs or systems
  • 5+ years industry experience of chip and/or computer architecture
  • 5+ years industry experience in Verilog or VHDL, C/C++, and scripting languages
  • Must pass Microsoft Cloud Background Check
  • Must meet export control regulations requirements

Benefits For Principal Design Verification Engineer

Medical Insurance
Education Budget
Parental Leave
  • Industry leading healthcare
  • Educational resources
  • Discounts on products and services
  • Savings and investments
  • Maternity and paternity leave
  • Generous time away
  • Giving programs
  • Opportunities to network and connect

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