Principal Silicon Design Engineer
Description For Principal Silicon Design Engineer
Microsoft's Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) team is seeking a Principal Silicon Design Engineer to join their innovative cloud infrastructure division. This role is crucial in developing and delivering operational excellence in hardware manufacturing for Microsoft's expanding cloud business. The position focuses on designing high-performance Network-on-Chip solutions for AI SoCs, requiring expertise in ASIC design, digital design, and system integration.
The ideal candidate will have extensive experience in silicon design, particularly in areas such as IP development, RTL coding, and system architecture. You'll be working with cutting-edge technology in AI and cloud infrastructure, contributing to Microsoft's mission of powering over 200 online businesses including Azure, Office 365, and Xbox Live.
This role offers a competitive salary range of $137,600 - $267,000 (higher in SF and NYC areas), along with comprehensive benefits including healthcare, educational resources, and parental leave. The position is hybrid-based in Mountain View, CA, with up to 50% work from home flexibility.
You'll be part of a team that values innovation, technical excellence, and collaborative problem-solving. This is an opportunity to shape the future of Microsoft's cloud infrastructure while working on challenging technical problems in AI and silicon design. The role requires strong technical skills, leadership abilities, and a passion for delivering customer-focused solutions in a fast-paced environment.
Responsibilities For Principal Silicon Design Engineer
- Drive high performance, high bandwidth Network-on-Chip designs in AI SoCs
- Work on IP microarchitecture specification, RTL design, synthesis, and SOC integration
- Interact with architecture, verification, and physical design teams
- Ensure design implementation and verification meets specifications
Requirements For Principal Silicon Design Engineer
- 9+ years of related technical engineering experience or equivalent combination of education and experience
- 6+ years of experience delivering successful IP or ASIC/SOC designs
- 6+ years expertise in Digital Design including microarchitecture specification development
- 6+ years of experience in Synthesis, Timing constraints, Power, Performance, Area trade-offs
- Experience with RTL coding in Verilog/System Verilog
- Pass Microsoft Cloud Background Check
- Meet export control regulations requirements
Benefits For Principal Silicon Design Engineer
- Industry leading healthcare
- Educational resources
- Discounts on products and services
- Savings and investments
- Maternity and paternity leave
- Generous time away
- Giving programs
- Opportunities to network and connect
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