Senior Analog Mask Layout Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering team powers Microsoft's online businesses and cloud infrastructure globally.
Embedded
Senior Software Engineer
Hybrid
5,000+ Employees
7+ years of experience
Enterprise SaaS · Hardware

Description For Senior Analog Mask Layout Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is seeking a Senior Analog Mask Layout Engineer to join their innovative team. This role is crucial in revolutionizing consumer electronic devices and Cloud Computing infrastructure. The position involves working on cutting-edge analog layout design, including high-speed CMOS Interface D2D, SERDES, and foundational analog blocks for next-generation Consumer & Cloud Computing Devices.

The ideal candidate will be part of the SCIPS Analog group, designing high-performance mixed signal ASICs in leading-edge CMOS technology. You'll work in a diverse, dynamic environment, collaborating with various teams to design and test products that power Microsoft's global infrastructure. The role requires a self-starter mentality and excellent technical and interpersonal skills.

As a Senior Analog Mask Layout Engineer, you'll be responsible for implementing complex analog designs, working with state-of-the-art EDA tools, and delivering complete layouts to customers. The position offers the opportunity to work on challenging projects using deep finfet design nodes and requires expertise in analog layout techniques such as common-centroid layout, matching, and thermal aware layouts.

This is an excellent opportunity for experienced professionals looking to make a significant impact in Microsoft's silicon development initiatives. The role offers a hybrid work environment with up to 50% work from home flexibility, comprehensive benefits, and the chance to work with cutting-edge technology in a global tech leader.

Last updated 2 hours ago

Responsibilities For Senior Analog Mask Layout Engineer

  • Execute Analog Mask Layout Design for high-performance IP designs
  • Work with Microsoft employees and contractors
  • Use Cadence Virtuoso design tools and flows
  • Deliver Analog IPs from schematic to GDS
  • Provide technical guidance to junior team members

Requirements For Senior Analog Mask Layout Engineer

  • 5-7 years of Analog Mask Layout execution and IP delivery experience
  • Experience with mass production Analog Layouts delivery
  • Detailed knowledge of EDA tools (Cadence, Mentor, Synopsys)
  • Experience with high-performance analog blocks (VCOs, Charge-Pumps, PLLs, etc.)
  • Knowledge of analog layout techniques
  • Experience with deep finfet design nodes
  • Good interpersonal skills
  • Must pass Microsoft Cloud Background Check

Benefits For Senior Analog Mask Layout Engineer

Medical Insurance
Education Budget
Parental Leave
  • Industry leading healthcare
  • Educational resources
  • Discounts on products and services
  • Savings and investments
  • Maternity and paternity leave
  • Generous time away
  • Giving programs
  • Opportunities to network and connect

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