Senior Design Verification Engineer

Microsoft's Silicon Architecture and Verification team is seeking a Senior Design Verification Engineer to work with cross-discipline teams to develop environment and test cases to verify hardware security designs. The candidate should be passionate about developing systematic and efficient methods to detect hardware/software vulnerabilities. The team is involved in numerous projects within Microsoft, developing custom silicon for a diverse set of systems ranging from innovative high-performance consumer products to Azure and Sphere IoT.

Responsibilities include:

• Planning verification of complex design IP/SoC, interacting with architecture and design engineers to identify verification test scenarios.
• Creating and enhancing constrained-random verification environments using SystemVerilog and UVM, or formally verifying designs with SVA and industry-leading formal tools.
• Developing tests using UVM or C/C++.
• Analyzing and debugging test failures with designers to deliver functionally correct designs.
• Identifying and writing functional coverage for stimulus and corner cases.
• Closing coverage to plug verification holes and meet tape-out requirements.

Required Qualifications:

• 7+ years of related technical engineering experience or equivalent combination of education and experience.
• 6+ years of experience in design verification with full verification cycle on complex SoC IPs and/or systems.
• Knowledge of verification principles, testbenches, stimulus generation, Verilog verification, and background in creating simulation environments, developing tests, and debugging designs.
• Good understanding of chip and/or computer architecture and experience writing tests in UVM, C, and C++.

Preferred Qualifications:

• Experience in hardware security IP and SOC level verification.
• Experience with secure hardware design for embedded systems.
• Firmware development experience, with secure and non-secure boot flow.
• Experience with hardware emulation or FPGAs.
• Experience in RTL design for FPGA or emulation.
• Experience in Assembly, startup code, and linker scripts.
• Experience in developing makefiles for software development.
• Scripting language such as Python, Ruby, or Perl.

The role offers competitive compensation and benefits, including industry-leading healthcare, educational resources, discounts on products and services, savings and investments, maternity and paternity leave, generous time away, giving programs, and opportunities to network and connect.

Microsoft is an equal opportunity employer and values diversity in its workforce.