Senior Design Verification Engineer
Description For Senior Design Verification Engineer
Microsoft's Silicon Architecture and Verification team is seeking a Senior Design Verification Engineer to join their innovative hardware security team. This role is part of Microsoft's Artificial Intelligence Silicon Engineering (AISiE) team, focusing on delivering cutting-edge custom IP and SoC designs. The position offers a unique opportunity to work on diverse projects ranging from high-performance consumer products to Azure and Sphere IoT solutions.
The role involves working with cross-discipline teams to develop verification environments and test cases for hardware security designs. You'll be responsible for ensuring the quality and security of hardware designs through systematic verification methods. The position requires expertise in design verification, hardware security, and programming skills in various languages including SystemVerilog, UVM, and C++.
Microsoft offers a competitive compensation package with a base salary range of $117,200 - $229,200, comprehensive benefits, and a hybrid work environment allowing up to 50% work from home. The company's culture emphasizes growth mindset, innovation, and collaboration, making it an ideal place for professionals passionate about advancing technology and making a global impact.
This is an excellent opportunity for experienced verification engineers who want to work on cutting-edge silicon projects while contributing to Microsoft's mission of empowering every person and organization on the planet to achieve more.
Responsibilities For Senior Design Verification Engineer
- Plan verification of complex design IP/SoC interacting with architecture and design engineers
- Create and enhance constrained-random verification environments using SystemVerilog and UVM
- Develop tests using UVM or C/C++
- Analyse and debug test failures with designers
- Identify and write functional coverage for stimulus and corner cases
- Close coverage to plug verification holes and meet tape out requirements
Requirements For Senior Design Verification Engineer
- 7+ years of related technical engineering experience or equivalent education
- 6+ years of experience in design verification with full verification cycle on complex SoC IPs and/or systems
- Knowledge of verification principles, testbenches, stimulus generation, Verilog verification
- Good understanding of chip and/or computer architecture
- Experience writing tests in UVM, C and C++
- Must pass Microsoft Cloud Background Check
- Must be eligible to access export-controlled information
Benefits For Senior Design Verification Engineer
- Industry leading healthcare
- Educational resources
- Discounts on products and services
- Savings and investments
- Maternity and paternity leave
- Generous time away
- Giving programs
- Opportunities to network and connect
